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target/ppc: Rename access_type to type in mmu_helper.c
The variable that holds ACCESS_INT, ACCESS_FLOAT, etc is variously called 'int type' or 'int access_type' within this file. Standardize on 'int type' throughout. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-6-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson
David Gibson
parent
31fa64ecfd
commit
352e3627b2
@ -126,11 +126,11 @@ static int pp_check(int key, int pp, int nx)
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return access;
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}
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static int check_prot(int prot, int rw, int access_type)
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static int check_prot(int prot, int rw, int type)
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{
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int ret;
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if (access_type == ACCESS_CODE) {
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if (type == ACCESS_CODE) {
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if (prot & PAGE_EXEC) {
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ret = 0;
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} else {
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@ -309,7 +309,7 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
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}
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static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int access_type)
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target_ulong eaddr, int rw, int type)
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{
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ppc6xx_tlb_t *tlb;
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int nr, best, way;
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@ -319,7 +319,7 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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ret = -1; /* No TLB found */
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for (way = 0; way < env->nb_ways; way++) {
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nr = ppc6xx_tlb_getnum(env, eaddr, way,
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access_type == ACCESS_CODE ? 1 : 0);
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type == ACCESS_CODE ? 1 : 0);
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tlb = &env->tlb.tlb6[nr];
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/* This test "emulates" the PTE index match for hardware TLBs */
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if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
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@ -333,9 +333,9 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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tlb->EPN, eaddr, tlb->pte1,
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rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
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rw ? 'S' : 'L', type == ACCESS_CODE ? 'I' : 'D');
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switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1,
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0, rw, access_type)) {
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0, rw, type)) {
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case -3:
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/* TLB inconsistency */
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return -1;
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@ -683,7 +683,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
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static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong address, int rw,
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int access_type)
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int type)
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{
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ppcemb_tlb_t *tlb;
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hwaddr raddr;
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@ -727,7 +727,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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check_perms:
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/* Check from TLB entry */
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ctx->prot = tlb->prot;
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ret = check_prot(ctx->prot, rw, access_type);
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ret = check_prot(ctx->prot, rw, type);
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if (ret == -2) {
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env->spr[SPR_40x_ESR] = 0;
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}
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@ -760,7 +760,7 @@ void store_40x_sler(CPUPPCState *env, uint32_t val)
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static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
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hwaddr *raddr, int *prot,
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target_ulong address, int rw,
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int access_type, int i)
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int type, int i)
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{
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int ret, prot2;
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@ -794,7 +794,7 @@ found_tlb:
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}
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/* Check the address space */
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if (access_type == ACCESS_CODE) {
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if (type == ACCESS_CODE) {
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if (msr_ir != (tlb->attr & 1)) {
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LOG_SWTLB("%s: AS doesn't match\n", __func__);
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return -1;
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@ -829,7 +829,7 @@ found_tlb:
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static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong address, int rw,
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int access_type)
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int type)
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{
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ppcemb_tlb_t *tlb;
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hwaddr raddr;
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@ -840,7 +840,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb.tlbe[i];
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ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
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access_type, i);
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type, i);
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if (ret != -1) {
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break;
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}
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@ -984,7 +984,7 @@ static bool mmubooke206_get_as(CPUPPCState *env,
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static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
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hwaddr *raddr, int *prot,
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target_ulong address, int rw,
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int access_type, int mmu_idx)
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int type, int mmu_idx)
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{
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int ret;
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int prot2 = 0;
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@ -1043,7 +1043,7 @@ found_tlb:
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}
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/* Check the address space and permissions */
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if (access_type == ACCESS_CODE) {
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if (type == ACCESS_CODE) {
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/* There is no way to fetch code using epid load */
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assert(!use_epid);
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if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
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@ -1080,7 +1080,7 @@ found_tlb:
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static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong address, int rw,
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int access_type, int mmu_idx)
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int type, int mmu_idx)
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{
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ppcmas_tlb_t *tlb;
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hwaddr raddr;
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@ -1098,7 +1098,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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continue;
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}
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ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
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rw, access_type, mmu_idx);
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rw, type, mmu_idx);
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if (ret != -1) {
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goto found_tlb;
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}
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@ -1415,12 +1415,12 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
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static int get_physical_address_wtlb(
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CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int access_type,
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target_ulong eaddr, int rw, int type,
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int mmu_idx)
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{
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int ret = -1;
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bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
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|| (access_type != ACCESS_CODE && msr_dr == 0);
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bool real_mode = (type == ACCESS_CODE && msr_ir == 0)
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|| (type != ACCESS_CODE && msr_dr == 0);
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switch (env->mmu_model) {
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case POWERPC_MMU_SOFT_6xx:
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@ -1430,11 +1430,11 @@ static int get_physical_address_wtlb(
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} else {
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/* Try to find a BAT */
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if (env->nb_BATs != 0) {
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ret = get_bat_6xx_tlb(env, ctx, eaddr, rw, access_type);
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ret = get_bat_6xx_tlb(env, ctx, eaddr, rw, type);
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}
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if (ret < 0) {
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/* We didn't match any BAT entry or don't have BATs */
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ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, access_type);
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ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, type);
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}
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}
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break;
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@ -1445,16 +1445,16 @@ static int get_physical_address_wtlb(
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ret = check_physical(env, ctx, eaddr, rw);
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} else {
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ret = mmu40x_get_physical_address(env, ctx, eaddr,
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rw, access_type);
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rw, type);
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}
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break;
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case POWERPC_MMU_BOOKE:
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ret = mmubooke_get_physical_address(env, ctx, eaddr,
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rw, access_type);
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rw, type);
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break;
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case POWERPC_MMU_BOOKE206:
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ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
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access_type, mmu_idx);
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type, mmu_idx);
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break;
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case POWERPC_MMU_MPC8xx:
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/* XXX: TODO */
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@ -1478,9 +1478,9 @@ static int get_physical_address_wtlb(
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static int get_physical_address(
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CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int access_type)
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target_ulong eaddr, int rw, int type)
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{
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return get_physical_address_wtlb(env, ctx, eaddr, rw, access_type, 0);
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return get_physical_address_wtlb(env, ctx, eaddr, rw, type, 0);
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}
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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@ -1584,19 +1584,19 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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CPUState *cs = env_cpu(env);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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mmu_ctx_t ctx;
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int access_type;
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int type;
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int ret = 0;
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if (rw == 2) {
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/* code access */
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rw = 0;
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access_type = ACCESS_CODE;
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type = ACCESS_CODE;
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} else {
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/* data access */
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access_type = env->access_type;
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type = env->access_type;
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}
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ret = get_physical_address_wtlb(env, &ctx, address, rw,
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access_type, mmu_idx);
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type, mmu_idx);
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if (ret == 0) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
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@ -1604,7 +1604,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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ret = 0;
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} else if (ret < 0) {
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LOG_MMU_STATE(cs);
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if (access_type == ACCESS_CODE) {
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if (type == ACCESS_CODE) {
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switch (ret) {
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case -1:
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/* No matches in page tables or TLB */
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@ -1761,7 +1761,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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break;
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case -4:
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/* Direct store exception */
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switch (access_type) {
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switch (type) {
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case ACCESS_FLOAT:
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/* Floating point load/store */
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cs->exception_index = POWERPC_EXCP_ALIGN;
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