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arm: a9mpcore: Coreify the SCU
Split the SCU in a9mpcore out into its own object definition. mpcore is now just a container for the mpcore components. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Crosthwaite
Peter Maydell
parent
9595978292
commit
353575f095
122
hw/a9mpcore.c
122
hw/a9mpcore.c
@ -10,113 +10,17 @@
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#include "sysbus.h"
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/* A9MP private memory region. */
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typedef struct A9MPPrivState {
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SysBusDevice busdev;
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uint32_t scu_control;
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uint32_t scu_status;
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uint32_t num_cpu;
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MemoryRegion scu_iomem;
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MemoryRegion container;
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DeviceState *mptimer;
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DeviceState *wdt;
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DeviceState *gic;
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DeviceState *scu;
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uint32_t num_irq;
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} A9MPPrivState;
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static uint64_t a9_scu_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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A9MPPrivState *s = (A9MPPrivState *)opaque;
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switch (offset) {
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case 0x00: /* Control */
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return s->scu_control;
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case 0x04: /* Configuration */
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return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
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case 0x08: /* CPU Power Status */
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return s->scu_status;
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case 0x09: /* CPU status. */
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return s->scu_status >> 8;
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case 0x0a: /* CPU status. */
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return s->scu_status >> 16;
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case 0x0b: /* CPU status. */
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return s->scu_status >> 24;
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case 0x0c: /* Invalidate All Registers In Secure State */
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return 0;
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case 0x40: /* Filtering Start Address Register */
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case 0x44: /* Filtering End Address Register */
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/* RAZ/WI, like an implementation with only one AXI master */
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return 0;
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case 0x50: /* SCU Access Control Register */
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case 0x54: /* SCU Non-secure Access Control Register */
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/* unimplemented, fall through */
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default:
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return 0;
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}
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}
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static void a9_scu_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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A9MPPrivState *s = (A9MPPrivState *)opaque;
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uint32_t mask;
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uint32_t shift;
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switch (size) {
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case 1:
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mask = 0xff;
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break;
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case 2:
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mask = 0xffff;
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break;
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case 4:
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mask = 0xffffffff;
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break;
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default:
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fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
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size, (unsigned)offset);
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return;
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}
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switch (offset) {
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case 0x00: /* Control */
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s->scu_control = value & 1;
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break;
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case 0x4: /* Configuration: RO */
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break;
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case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
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shift = (offset - 0x8) * 8;
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s->scu_status &= ~(mask << shift);
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s->scu_status |= ((value & mask) << shift);
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break;
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case 0x0c: /* Invalidate All Registers In Secure State */
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/* no-op as we do not implement caches */
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break;
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case 0x40: /* Filtering Start Address Register */
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case 0x44: /* Filtering End Address Register */
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/* RAZ/WI, like an implementation with only one AXI master */
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break;
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case 0x50: /* SCU Access Control Register */
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case 0x54: /* SCU Non-secure Access Control Register */
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/* unimplemented, fall through */
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default:
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break;
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}
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}
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static const MemoryRegionOps a9_scu_ops = {
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.read = a9_scu_read,
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.write = a9_scu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void a9mp_priv_reset(DeviceState *dev)
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{
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A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, SYS_BUS_DEVICE(dev));
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s->scu_control = 0;
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}
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static void a9mp_priv_set_irq(void *opaque, int irq, int level)
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{
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A9MPPrivState *s = (A9MPPrivState *)opaque;
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@ -126,7 +30,7 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int level)
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static int a9mp_priv_init(SysBusDevice *dev)
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{
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A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev);
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SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev;
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SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
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int i;
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s->gic = qdev_create(NULL, "arm_gic");
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@ -141,6 +45,11 @@ static int a9mp_priv_init(SysBusDevice *dev)
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/* Pass through inbound GPIO lines to the GIC */
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qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32);
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s->scu = qdev_create(NULL, "a9-scu");
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qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu);
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qdev_init_nofail(s->scu);
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scubusdev = SYS_BUS_DEVICE(s->scu);
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s->mptimer = qdev_create(NULL, "arm_mptimer");
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qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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qdev_init_nofail(s->mptimer);
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@ -163,8 +72,8 @@ static int a9mp_priv_init(SysBusDevice *dev)
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* We should implement the global timer but don't currently do so.
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*/
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memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
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memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100);
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memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(scubusdev, 0));
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/* GIC CPU interface */
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memory_region_add_subregion(&s->container, 0x100,
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sysbus_mmio_get_region(gicbusdev, 1));
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@ -193,17 +102,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
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return 0;
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}
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static const VMStateDescription vmstate_a9mp_priv = {
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.name = "a9mpcore_priv",
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(scu_control, A9MPPrivState),
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VMSTATE_UINT32_V(scu_status, A9MPPrivState, 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property a9mp_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
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/* The Cortex-A9MP may have anything from 0 to 224 external interrupt
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@ -223,8 +121,6 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data)
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k->init = a9mp_priv_init;
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dc->props = a9mp_priv_properties;
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dc->vmsd = &vmstate_a9mp_priv;
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dc->reset = a9mp_priv_reset;
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}
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static const TypeInfo a9mp_priv_info = {
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164
hw/a9scu.c
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164
hw/a9scu.c
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@ -0,0 +1,164 @@
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/*
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* Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
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*
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* Copyright (c) 2009 CodeSourcery.
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* Copyright (c) 2011 Linaro Limited.
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* Written by Paul Brook, Peter Maydell.
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*
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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/* A9MP private memory region. */
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typedef struct A9SCUState {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t control;
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uint32_t status;
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uint32_t num_cpu;
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} A9SCUState;
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#define TYPE_A9_SCU "a9-scu"
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#define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU)
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static uint64_t a9_scu_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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A9SCUState *s = (A9SCUState *)opaque;
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switch (offset) {
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case 0x00: /* Control */
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return s->control;
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case 0x04: /* Configuration */
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return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
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case 0x08: /* CPU Power Status */
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return s->status;
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case 0x09: /* CPU status. */
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return s->status >> 8;
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case 0x0a: /* CPU status. */
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return s->status >> 16;
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case 0x0b: /* CPU status. */
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return s->status >> 24;
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case 0x0c: /* Invalidate All Registers In Secure State */
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return 0;
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case 0x40: /* Filtering Start Address Register */
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case 0x44: /* Filtering End Address Register */
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/* RAZ/WI, like an implementation with only one AXI master */
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return 0;
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case 0x50: /* SCU Access Control Register */
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case 0x54: /* SCU Non-secure Access Control Register */
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/* unimplemented, fall through */
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default:
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return 0;
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}
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}
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static void a9_scu_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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A9SCUState *s = (A9SCUState *)opaque;
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uint32_t mask;
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uint32_t shift;
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switch (size) {
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case 1:
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mask = 0xff;
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break;
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case 2:
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mask = 0xffff;
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break;
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case 4:
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mask = 0xffffffff;
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break;
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default:
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fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
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size, (unsigned)offset);
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return;
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}
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switch (offset) {
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case 0x00: /* Control */
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s->control = value & 1;
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break;
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case 0x4: /* Configuration: RO */
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break;
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case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
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shift = (offset - 0x8) * 8;
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s->status &= ~(mask << shift);
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s->status |= ((value & mask) << shift);
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break;
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case 0x0c: /* Invalidate All Registers In Secure State */
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/* no-op as we do not implement caches */
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break;
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case 0x40: /* Filtering Start Address Register */
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case 0x44: /* Filtering End Address Register */
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/* RAZ/WI, like an implementation with only one AXI master */
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break;
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case 0x50: /* SCU Access Control Register */
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case 0x54: /* SCU Non-secure Access Control Register */
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/* unimplemented, fall through */
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default:
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break;
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}
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}
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static const MemoryRegionOps a9_scu_ops = {
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.read = a9_scu_read,
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.write = a9_scu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void a9_scu_reset(DeviceState *dev)
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{
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A9SCUState *s = A9_SCU(dev);
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s->control = 0;
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}
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static void a9_scu_realize(DeviceState *dev, Error ** errp)
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{
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A9SCUState *s = A9_SCU(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->iomem, &a9_scu_ops, s, "a9-scu", 0x100);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_a9_scu = {
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.name = "a9-scu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(control, A9SCUState),
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VMSTATE_UINT32(status, A9SCUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property a9_scu_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", A9SCUState, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void a9_scu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = a9_scu_realize;
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dc->props = a9_scu_properties;
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dc->vmsd = &vmstate_a9_scu;
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dc->reset = a9_scu_reset;
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}
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static const TypeInfo a9_scu_info = {
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.name = TYPE_A9_SCU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(A9SCUState),
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.class_init = a9_scu_class_init,
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};
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static void a9mp_register_types(void)
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{
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type_register_static(&a9_scu_info);
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}
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type_init(a9mp_register_types)
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@ -3,6 +3,7 @@ obj-y += arm_boot.o
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obj-y += xilinx_zynq.o zynq_slcr.o
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obj-y += xilinx_spips.o
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obj-y += arm_gic.o arm_gic_common.o
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obj-y += a9scu.o
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obj-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
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obj-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
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obj-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
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