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target/arm: Convert Neon 2-reg-misc VREV64 to decodetree

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Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-06-16 18:08:24 +01:00
parent 2032e243a5
commit 353d2b8505
3 changed files with 64 additions and 22 deletions
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12
target/arm/neon-dp.decode
View File

@ -429,6 +429,18 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
vm=%vm_dp vd=%vd_dp size=1
VDUP_scalar 1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
vm=%vm_dp vd=%vd_dp size=2
##################################################################
# 2-reg-misc grouping:
# 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
##################################################################
&2misc vd vm q size
@2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
&2misc vm=%vm_dp vd=%vd_dp
VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
]
# Subgroup for size != 0b11

50
target/arm/translate-neon.inc.c
View File

@ -2970,3 +2970,53 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
a->q ? 16 : 8, a->q ? 16 : 8);
return true;
}
static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
{
int pass, half;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vm) & 0x10)) {
return false;
}
if ((a->vd | a->vm) & a->q) {
return false;
}
if (a->size == 3) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
TCGv_i32 tmp[2];
for (half = 0; half < 2; half++) {
tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
switch (a->size) {
case 0:
tcg_gen_bswap32_i32(tmp[half], tmp[half]);
break;
case 1:
gen_swap_half(tmp[half]);
break;
case 2:
break;
default:
g_assert_not_reached();
}
}
neon_store_reg(a->vd, pass * 2, tmp[1]);
neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
}
return true;
}

24
target/arm/translate.c
View File

@ -5092,28 +5092,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
switch (op) {
case NEON_2RM_VREV64:
for (pass = 0; pass < (q ? 2 : 1); pass++) {
tmp = neon_load_reg(rm, pass * 2);
tmp2 = neon_load_reg(rm, pass * 2 + 1);
switch (size) {
case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
case 1: gen_swap_half(tmp); break;
case 2: /* no-op */ break;
default: abort();
}
neon_store_reg(rd, pass * 2 + 1, tmp);
if (size == 2) {
neon_store_reg(rd, pass * 2, tmp2);
} else {
switch (size) {
case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
case 1: gen_swap_half(tmp2); break;
default: abort();
}
neon_store_reg(rd, pass * 2, tmp2);
}
}
break;
/* handled by decodetree */
return 1;
case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
for (pass = 0; pass < q + 1; pass++) {