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target-arm: A64: Add SIMD scalar copy instructions
Add support for the SIMD scalar copy instruction group (C3.6.7), which consists of the single instruction DUP (element, scalar). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -5108,6 +5108,35 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
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tcg_temp_free_i64(tmp);
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}
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/* C6.3.31 DUP (element, scalar)
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* 31 21 20 16 15 10 9 5 4 0
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* +-----------------------+--------+-------------+------+------+
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* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
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* +-----------------------+--------+-------------+------+------+
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*/
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static void handle_simd_dupes(DisasContext *s, int rd, int rn,
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int imm5)
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{
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int size = ctz32(imm5);
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int index;
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TCGv_i64 tmp;
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if (size > 3) {
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unallocated_encoding(s);
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return;
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}
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index = imm5 >> (size + 1);
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/* This instruction just extracts the specified element and
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* zero-extends it into the bottom of the destination register.
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*/
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tmp = tcg_temp_new_i64();
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read_vec_element(s, tmp, rn, index, size);
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write_fp_dreg(s, rd, tmp);
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tcg_temp_free_i64(tmp);
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}
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/* C6.3.32 DUP (General)
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*
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* 31 30 29 21 20 16 15 10 9 5 4 0
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@ -5425,7 +5454,19 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
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*/
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static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int imm4 = extract32(insn, 11, 4);
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int imm5 = extract32(insn, 16, 5);
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int op = extract32(insn, 29, 1);
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if (op != 0 || imm4 != 0) {
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unallocated_encoding(s);
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return;
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}
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/* DUP (element, scalar) */
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handle_simd_dupes(s, rd, rn, imm5);
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}
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/* C3.6.8 AdvSIMD scalar pairwise
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