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FDC fix 4/10 (Hervé Poussineau):
- Handles correctly FD_MSR_NONDMA/FD_DOR_NONDMA flags, and uses them when possible. Fixes a problem with SPECIFY command. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4284 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
8c6a4d7742
commit
368df94d16
33
hw/fdc.c
33
hw/fdc.c
@ -494,6 +494,8 @@ struct fdctrl_t {
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QEMUTimer *result_timer;
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uint8_t sra;
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uint8_t srb;
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uint8_t dor;
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uint8_t msr;
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uint8_t state;
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uint8_t dma_en;
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uint8_t cur_drv;
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@ -771,6 +773,9 @@ static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
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if (!fdctrl->drives[1].bs)
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fdctrl->sra |= FD_SRA_nDRV2;
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fdctrl->cur_drv = 0;
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fdctrl->dor = 0;
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fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
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fdctrl->msr = 0;
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/* FIFO state */
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fdctrl->data_pos = 0;
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fdctrl->data_len = 0;
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@ -829,7 +834,7 @@ static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
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if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON)
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retval |= FD_DOR_MOTEN1;
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/* DMA enable */
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if (fdctrl->dma_en)
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if (fdctrl->dor & FD_DOR_DMAEN)
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retval |= FD_DOR_DMAEN;
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/* Reset indicator */
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if (!(fdctrl->state & FD_CTRL_RESET))
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@ -897,6 +902,8 @@ static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
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}
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/* Selected drive */
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fdctrl->cur_drv = value & FD_DOR_SELMASK;
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fdctrl->dor = value;
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}
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/* Tape drive register : 0x03 */
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@ -1085,10 +1092,11 @@ static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
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fdctrl->fifo[5] = cur_drv->sect;
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fdctrl->fifo[6] = FD_SECTOR_SC;
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fdctrl->data_dir = FD_DIR_READ;
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if (fdctrl->state & FD_CTRL_BUSY) {
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if (!(fdctrl->msr & FD_MSR_NONDMA)) {
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DMA_release_DREQ(fdctrl->dma_chann);
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fdctrl->state &= ~FD_CTRL_BUSY;
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}
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fdctrl->msr &= ~FD_MSR_NONDMA;
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fdctrl_set_fifo(fdctrl, 7, 1);
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}
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@ -1159,7 +1167,7 @@ static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
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fdctrl->data_len *= tmp;
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}
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fdctrl->eot = fdctrl->fifo[6];
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if (fdctrl->dma_en) {
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if (fdctrl->dor & FD_DOR_DMAEN) {
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int dma_mode;
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/* DMA transfer are enabled. Check if DMA channel is well programmed */
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dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
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@ -1185,6 +1193,7 @@ static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
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}
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}
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FLOPPY_DPRINTF("start non-DMA transfer\n");
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fdctrl->msr |= FD_MSR_NONDMA;
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/* IO based transfer: calculate len */
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fdctrl_raise_irq(fdctrl, 0x00);
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@ -1325,7 +1334,7 @@ static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
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return 0;
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}
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pos = fdctrl->data_pos;
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if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
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if (fdctrl->msr & FD_MSR_NONDMA) {
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pos %= FD_SECTOR_LEN;
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if (pos == 0) {
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if (fdctrl->data_pos != 0)
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@ -1343,7 +1352,7 @@ static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
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/* Switch from transfer mode to status mode
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* then from status mode to command mode
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*/
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if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
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if (fdctrl->msr & FD_MSR_NONDMA) {
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fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
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} else {
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fdctrl_reset_fifo(fdctrl);
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@ -1438,7 +1447,7 @@ static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
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fdctrl->fifo[3] = 0;
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/* timers */
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fdctrl->fifo[4] = fdctrl->timer0;
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fdctrl->fifo[5] = (fdctrl->timer1 << 1) | fdctrl->dma_en;
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fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
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fdctrl->fifo[6] = cur_drv->last_sect;
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fdctrl->fifo[7] = (fdctrl->lock << 7) |
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(cur_drv->perpendicular << 2);
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@ -1547,7 +1556,10 @@ static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
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{
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fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
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fdctrl->timer1 = fdctrl->fifo[2] >> 1;
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fdctrl->dma_en = 1 - (fdctrl->fifo[2] & 1) ;
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if (fdctrl->fifo[2] & 1)
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fdctrl->dor &= ~FD_DOR_DMAEN;
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else
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fdctrl->dor |= FD_DOR_DMAEN;
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/* No result back */
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fdctrl_reset_fifo(fdctrl);
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}
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@ -1770,7 +1782,7 @@ static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
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return;
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}
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/* Is it write command time ? */
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if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
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if (fdctrl->msr & FD_MSR_NONDMA) {
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/* FIFO data write */
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fdctrl->fifo[fdctrl->data_pos++] = value;
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if (fdctrl->data_pos % FD_SECTOR_LEN == (FD_SECTOR_LEN - 1) ||
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@ -1862,10 +1874,7 @@ static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
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fdctrl->io_base = io_base;
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fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
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if (fdctrl->dma_chann != -1) {
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fdctrl->dma_en = 1;
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DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
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} else {
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fdctrl->dma_en = 0;
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}
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for (i = 0; i < MAX_FD; i++) {
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fd_init(&fdctrl->drives[i], fds[i]);
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@ -1915,7 +1924,7 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
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fdctrl_t *fdctrl;
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int io_mem;
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fdctrl = fdctrl_init_common(irq, 0, io_base, fds);
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fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
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fdctrl->sun4m = 1;
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io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
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fdctrl_mem_write_strict,
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