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target-tilegx: Implement v1multu instruction
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1442874414-3578-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -5,6 +5,7 @@ DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
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DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
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DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
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DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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@ -28,6 +28,19 @@
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#define V2(X) (((X) & 0xffff) * 0x0001000100010001ull)
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uint64_t helper_v1multu(uint64_t a, uint64_t b)
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{
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uint64_t r = 0;
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int i;
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for (i = 0; i < 64; i += 8) {
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unsigned ae = extract64(a, i, 8);
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unsigned be = extract64(b, i, 8);
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r = deposit64(r, i, 8, ae * be);
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}
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return r;
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}
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uint64_t helper_v1shl(uint64_t a, uint64_t b)
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{
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uint64_t m;
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@ -1155,7 +1155,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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case OE_RRR(V1MINU, 0, X1):
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case OE_RRR(V1MNZ, 0, X0):
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case OE_RRR(V1MNZ, 0, X1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RRR(V1MULTU, 0, X0):
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gen_helper_v1multu(tdest, tsrca, tsrcb);
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mnemonic = "v1multu";
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break;
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case OE_RRR(V1MULUS, 0, X0):
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case OE_RRR(V1MULU, 0, X0):
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case OE_RRR(V1MZ, 0, X0):
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