diff --git a/cpu-exec.c b/cpu-exec.c index 5a4399509e..30cfa2a63a 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -681,6 +681,10 @@ int cpu_exec(CPUArchState *env) * local variables as longjmp is marked 'noreturn'. */ cpu = current_cpu; env = cpu->env_ptr; +#if !(defined(CONFIG_USER_ONLY) && \ + (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X))) + cc = CPU_GET_CLASS(cpu); +#endif } } /* for(;;) */ diff --git a/cputlb.c b/cputlb.c index 19ecf60983..fff0afbd4a 100644 --- a/cputlb.c +++ b/cputlb.c @@ -169,21 +169,6 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) return ram_addr; } -static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) -{ - ram_addr_t ram_addr; - void *p; - - if (tlb_is_dirty_ram(tlb_entry)) { - p = (void *)(uintptr_t)((tlb_entry->addr_write & TARGET_PAGE_MASK) - + tlb_entry->addend); - ram_addr = qemu_ram_addr_from_host_nofail(p); - if (!cpu_physical_memory_is_dirty(ram_addr)) { - tlb_entry->addr_write |= TLB_NOTDIRTY; - } - } -} - void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length) { CPUState *cpu; diff --git a/exec.c b/exec.c index 51c23692fb..35ce8329e1 100644 --- a/exec.c +++ b/exec.c @@ -625,38 +625,6 @@ void cpu_abort(CPUArchState *env, const char *fmt, ...) abort(); } -CPUArchState *cpu_copy(CPUArchState *env) -{ - CPUArchState *new_env = cpu_init(env->cpu_model_str); -#if defined(TARGET_HAS_ICE) - CPUBreakpoint *bp; - CPUWatchpoint *wp; -#endif - - /* Reset non arch specific state */ - cpu_reset(ENV_GET_CPU(new_env)); - - /* Copy arch specific state into the new CPU */ - memcpy(new_env, env, sizeof(CPUArchState)); - - /* Clone all break/watchpoints. - Note: Once we support ptrace with hw-debug register access, make sure - BP_CPU break/watchpoints are handled correctly on clone. */ - QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); -#if defined(TARGET_HAS_ICE) - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { - cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); - } - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { - cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, - wp->flags, NULL); - } -#endif - - return new_env; -} - #if !defined(CONFIG_USER_ONLY) static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end, uintptr_t length) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index a5c028c536..01cd8c7a2b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -178,7 +178,5 @@ typedef struct CPUWatchpoint { \ /* user data */ \ void *opaque; \ - \ - const char *cpu_model_str; #endif diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 9b2ddc4acc..6083839084 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -230,6 +230,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); .driver = "e1000",\ .property = "mitigation",\ .value = "off",\ + },{\ + .driver = "qemu64-" TYPE_X86_CPU,\ + .property = "model",\ + .value = stringify(2),\ + },{\ + .driver = "qemu32-" TYPE_X86_CPU,\ + .property = "model",\ + .value = stringify(3),\ } #define PC_COMPAT_1_5 \ diff --git a/linux-user/main.c b/linux-user/main.c index 1561950bf5..6b4ab0930e 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -42,7 +42,7 @@ const char *filename; const char *argv0; int gdbstub_port; envlist_t *envlist; -const char *cpu_model; +static const char *cpu_model; unsigned long mmap_min_addr; #if defined(CONFIG_USE_GUEST_BASE) unsigned long guest_base; @@ -3285,6 +3285,37 @@ void init_task_state(TaskState *ts) ts->sigqueue_table[i].next = NULL; } +CPUArchState *cpu_copy(CPUArchState *env) +{ + CPUArchState *new_env = cpu_init(cpu_model); +#if defined(TARGET_HAS_ICE) + CPUBreakpoint *bp; + CPUWatchpoint *wp; +#endif + + /* Reset non arch specific state */ + cpu_reset(ENV_GET_CPU(new_env)); + + memcpy(new_env, env, sizeof(CPUArchState)); + + /* Clone all break/watchpoints. + Note: Once we support ptrace with hw-debug register access, make sure + BP_CPU break/watchpoints are handled correctly on clone. */ + QTAILQ_INIT(&env->breakpoints); + QTAILQ_INIT(&env->watchpoints); +#if defined(TARGET_HAS_ICE) + QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); + } + QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, + wp->flags, NULL); + } +#endif + + return new_env; +} + static void handle_arg_help(const char *arg) { usage(); diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index cfad2ea121..a0d5d5bd93 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -131,7 +131,6 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) AlphaCPU *cpu_alpha_init(const char *cpu_model) { AlphaCPU *cpu; - CPUAlphaState *env; ObjectClass *cpu_class; cpu_class = alpha_cpu_class_by_name(cpu_model); @@ -140,9 +139,6 @@ AlphaCPU *cpu_alpha_init(const char *cpu_model) cpu_class = object_class_by_name(TYPE("ev67")); } cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class))); - env = &cpu->env; - - env->cpu_model_str = cpu_model; object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target-arm/helper.c b/target-arm/helper.c index 2a98be7436..c63bbd7fc1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1749,7 +1749,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPU *cpu_arm_init(const char *cpu_model) { ARMCPU *cpu; - CPUARMState *env; ObjectClass *oc; oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); @@ -1757,8 +1756,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model) return NULL; } cpu = ARM_CPU(object_new(object_class_get_name(oc))); - env = &cpu->env; - env->cpu_model_str = cpu_model; /* TODO this should be set centrally, once possible */ object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b6828022bc..d0c9bdb629 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -545,7 +545,7 @@ static x86_def_t builtin_x86_defs[] = { .level = 4, .vendor = CPUID_VENDOR_AMD, .family = 6, - .model = 2, + .model = 6, .stepping = 3, .features[FEAT_1_EDX] = PPRO_FEATURES | @@ -648,7 +648,7 @@ static x86_def_t builtin_x86_defs[] = { .level = 4, .vendor = CPUID_VENDOR_INTEL, .family = 6, - .model = 3, + .model = 6, .stepping = 3, .features[FEAT_1_EDX] = PPRO_FEATURES, @@ -1899,7 +1899,6 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge, Error **errp) { X86CPU *cpu = NULL; - CPUX86State *env; gchar **model_pieces; char *name, *features; char *typename; @@ -1922,8 +1921,6 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge, qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); object_unref(OBJECT(cpu)); #endif - env = &cpu->env; - env->cpu_model_str = cpu_model; cpu_x86_register(cpu, name, &error); if (error) { diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 00a7a08e83..a8f32fc88b 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -110,7 +110,6 @@ M68kCPU *cpu_m68k_init(const char *cpu_model) } cpu = M68K_CPU(object_new(object_class_get_name(oc))); env = &cpu->env; - env->cpu_model_str = cpu_model; register_m68k_insns(env); diff --git a/target-mips/translate.c b/target-mips/translate.c index ad43d59103..dea3956c60 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15907,7 +15907,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU)); env = &cpu->env; env->cpu_model = def; - env->cpu_model_str = cpu_model; #ifndef CONFIG_USER_ONLY mmu_init(env, def); diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index d97a091eb4..484ecc2124 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -138,7 +138,6 @@ MoxieCPU *cpu_moxie_init(const char *cpu_model) return NULL; } cpu = MOXIE_CPU(object_new(object_class_get_name(oc))); - cpu->env.cpu_model_str = cpu_model; object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 075f00a897..813794300b 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -209,7 +209,6 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) return NULL; } cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); - cpu->env.cpu_model_str = cpu_model; object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index d2645bad28..651da6b0d5 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8267,7 +8267,6 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name) PowerPCCPU *cpu_ppc_init(const char *cpu_model) { PowerPCCPU *cpu; - CPUPPCState *env; ObjectClass *oc; Error *err = NULL; @@ -8277,8 +8276,6 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model) } cpu = POWERPC_CPU(object_new(object_class_get_name(oc))); - env = &cpu->env; - env->cpu_model_str = cpu_model; object_property_set_bool(OBJECT(cpu), true, "realized", &err); if (err != NULL) { diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 61abfd7d9e..da33b38009 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -73,11 +73,8 @@ void s390x_cpu_timer(void *opaque) S390CPU *cpu_s390x_init(const char *cpu_model) { S390CPU *cpu; - CPUS390XState *env; cpu = S390_CPU(object_new(TYPE_S390_CPU)); - env = &cpu->env; - env->cpu_model_str = cpu_model; object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 34b2b57ba7..c23294d410 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -144,7 +144,6 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) SuperHCPU *cpu_sh4_init(const char *cpu_model) { SuperHCPU *cpu; - CPUSH4State *env; ObjectClass *oc; oc = superh_cpu_class_by_name(cpu_model); @@ -152,8 +151,6 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model) return NULL; } cpu = SUPERH_CPU(object_new(object_class_get_name(oc))); - env = &cpu->env; - env->cpu_model_str = cpu_model; object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 47ce60de4a..e7f878ee81 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -84,7 +84,6 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) env->def->features |= CPU_FEATURE_FLOAT128; } #endif - env->cpu_model_str = cpu_model; env->version = def->iu_version; env->fsr = def->fpu_version; env->nwindows = def->nwindows; diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index 61eb2c374a..9bf4fea5db 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -37,7 +37,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model) } cpu = UNICORE32_CPU(object_new(object_class_get_name(oc))); env = &cpu->env; - env->cpu_model_str = cpu_model; object_property_set_bool(OBJECT(cpu), true, "realized", NULL);