target-xtensa: update EXCVADDR in case of page table lookup

According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, even
if the miss is handled entirely by processor hardware.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Max Filippov 2012-05-27 18:34:50 +04:00 committed by Blue Swirl
parent e323bdeff2
commit 39e7d37f0f

View File

@ -511,6 +511,7 @@ static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
*wi = (++env->autorefill_idx) & 0x3;
split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei);
xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte);
env->sregs[EXCVADDR] = vaddr;
qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
__func__, vaddr, vpn, pte);
}