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target/arm: Fix alignment for VLD4.32

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When requested, the alignment for VLD4.32 is 8 and not 16.

See ARM documentation about VLD4 encoding:
    ebytes = 1 << UInt(size);
    if size == '10' then
        alignment = if a == '0' then 1 else 8;
    else
        alignment = if a == '0' then 1 else 4*ebytes;

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220914105058.2787404-1-chigot@adacore.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Clément Chigot 2022-09-14 12:50:59 +02:00 committed by Peter Maydell
parent fb96d131ee
commit 3a661024cc
1 changed files with 5 additions and 1 deletions
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6
target/arm/translate-neon.c
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@ -584,7 +584,11 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
case 3:
return false;
case 4:
align = pow2_align(size + 2);
if (size == 2) {
align = pow2_align(3);
} else {
align = pow2_align(size + 2);
}
break;
default:
g_assert_not_reached();