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hw/unicore32/puv3: Use qemu_log_mask(ERROR) instead of debug printf()

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Replace some debug printf() calls by qemu_log_mask(LOG_GUEST_ERROR).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20200524164503.11944-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Philippe Mathieu-Daudé 2020-05-24 18:45:03 +02:00 committed by Laurent Vivier
parent 449fd1fc00
commit 3b34ee6780
6 changed files with 39 additions and 14 deletions
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9
hw/dma/puv3_dma.c
View File

@ -15,6 +15,7 @@
#undef DEBUG_PUV3 #undef DEBUG_PUV3
#include "hw/unicore32/puv3.h" #include "hw/unicore32/puv3.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/log.h"
#define PUV3_DMA_CH_NR (6) #define PUV3_DMA_CH_NR (6)
#define PUV3_DMA_CH_MASK (0xff) #define PUV3_DMA_CH_MASK (0xff)
@ -43,7 +44,9 @@ static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
ret = s->reg_CFG[PUV3_DMA_CH(offset)]; ret = s->reg_CFG[PUV3_DMA_CH(offset)];
break; break;
default: default:
DPRINTF("Bad offset 0x%x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
@ -62,7 +65,9 @@ static void puv3_dma_write(void *opaque, hwaddr offset,
s->reg_CFG[PUV3_DMA_CH(offset)] = value; s->reg_CFG[PUV3_DMA_CH(offset)] = value;
break; break;
default: default:
DPRINTF("Bad offset 0x%x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
DPRINTF("offset 0x%x, value 0x%x\n", offset, value); DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
} }

15
hw/gpio/puv3_gpio.c
View File

@ -15,6 +15,7 @@
#undef DEBUG_PUV3 #undef DEBUG_PUV3
#include "hw/unicore32/puv3.h" #include "hw/unicore32/puv3.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/log.h"
#define TYPE_PUV3_GPIO "puv3_gpio" #define TYPE_PUV3_GPIO "puv3_gpio"
#define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO) #define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
@ -47,7 +48,9 @@ static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
ret = s->reg_GPIR; ret = s->reg_GPIR;
break; break;
default: default:
DPRINTF("Bad offset 0x%x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
@ -68,14 +71,16 @@ static void puv3_gpio_write(void *opaque, hwaddr offset,
if (s->reg_GPDR & value) { if (s->reg_GPDR & value) {
s->reg_GPLR |= value; s->reg_GPLR |= value;
} else { } else {
DPRINTF("Write gpio input port error!"); qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
__func__);
} }
break; break;
case 0x0c: case 0x0c:
if (s->reg_GPDR & value) { if (s->reg_GPDR & value) {
s->reg_GPLR &= ~value; s->reg_GPLR &= ~value;
} else { } else {
DPRINTF("Write gpio input port error!"); qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
__func__);
} }
break; break;
case 0x10: /* GRER */ case 0x10: /* GRER */
@ -86,7 +91,9 @@ static void puv3_gpio_write(void *opaque, hwaddr offset,
s->reg_GPIR = value; s->reg_GPIR = value;
break; break;
default: default:
DPRINTF("Bad offset 0x%x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
} }

9
hw/intc/puv3_intc.c
View File

@ -16,6 +16,7 @@
#undef DEBUG_PUV3 #undef DEBUG_PUV3
#include "hw/unicore32/puv3.h" #include "hw/unicore32/puv3.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/log.h"
#define TYPE_PUV3_INTC "puv3_intc" #define TYPE_PUV3_INTC "puv3_intc"
#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC) #define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
@ -68,7 +69,9 @@ static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
ret = s->reg_ICPR; /* the same value with ICPR */ ret = s->reg_ICPR; /* the same value with ICPR */
break; break;
default: default:
DPRINTF("Bad offset %x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret; return ret;
@ -88,7 +91,9 @@ static void puv3_intc_write(void *opaque, hwaddr offset,
s->reg_ICMR = value; s->reg_ICMR = value;
break; break;
default: default:
DPRINTF("Bad offset 0x%x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
return; return;
} }
puv3_intc_update(s); puv3_intc_update(s);

9
hw/misc/puv3_pm.c
View File

@ -15,6 +15,7 @@
#undef DEBUG_PUV3 #undef DEBUG_PUV3
#include "hw/unicore32/puv3.h" #include "hw/unicore32/puv3.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/log.h"
#define TYPE_PUV3_PM "puv3_pm" #define TYPE_PUV3_PM "puv3_pm"
#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM) #define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
@ -73,7 +74,9 @@ static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
ret = 0x7; ret = 0x7;
break; break;
default: default:
DPRINTF("Bad offset 0x%x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
@ -105,7 +108,9 @@ static void puv3_pm_write(void *opaque, hwaddr offset,
case 0x38: case 0x38:
break; break;
default: default:
DPRINTF("Bad offset 0x%x\n", offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
DPRINTF("offset 0x%x, value 0x%x\n", offset, value); DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
} }

9
hw/timer/puv3_ost.c
View File

@ -14,6 +14,7 @@
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/ptimer.h" #include "hw/ptimer.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "qemu/log.h"
#undef DEBUG_PUV3 #undef DEBUG_PUV3
#include "hw/unicore32/puv3.h" #include "hw/unicore32/puv3.h"
@ -52,7 +53,9 @@ static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
ret = s->reg_OIER; ret = s->reg_OIER;
break; break;
default: default:
DPRINTF("Bad offset %x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret; return ret;
@ -88,7 +91,9 @@ static void puv3_ost_write(void *opaque, hwaddr offset,
s->reg_OIER = value; s->reg_OIER = value;
break; break;
default: default:
DPRINTF("Bad offset %x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
__func__, offset);
} }
} }

2
hw/unicore32/puv3.c
View File

@ -16,8 +16,6 @@
#include "hw/boards.h" #include "hw/boards.h"
#include "hw/loader.h" #include "hw/loader.h"
#include "sysemu/qtest.h" #include "sysemu/qtest.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h" #include "hw/unicore32/puv3.h"
#include "hw/input/i8042.h" #include "hw/input/i8042.h"
#include "hw/irq.h" #include "hw/irq.h"