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target/arm: Use unallocated_encoding for aarch32
Promote this function from aarch64 to fully general use. Use it to unify the code sequences for generating illegal opcode exceptions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190807045335.1361-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -338,13 +338,6 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
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}
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}
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void unallocated_encoding(DisasContext *s)
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{
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/* Unallocated and reserved encodings are uncategorized */
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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}
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static void init_tmp_a64_array(DisasContext *s)
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{
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#ifdef CONFIG_DEBUG_TCG
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@ -18,8 +18,6 @@
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#ifndef TARGET_ARM_TRANSLATE_A64_H
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#define TARGET_ARM_TRANSLATE_A64_H
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void unallocated_encoding(DisasContext *s);
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#define unsupported_encoding(s, insn) \
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do { \
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qemu_log_mask(LOG_UNIMP, \
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@ -108,8 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
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if (!s->vfp_enabled && !ignore_vfp_enabled) {
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assert(!arm_dc_feature(s, ARM_FEATURE_M));
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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unallocated_encoding(s);
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return false;
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}
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@ -1270,6 +1270,13 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
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s->base.is_jmp = DISAS_NORETURN;
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}
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void unallocated_encoding(DisasContext *s)
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{
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/* Unallocated and reserved encodings are uncategorized */
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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}
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/* Force a TB lookup after an instruction that changes the CPU state. */
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static inline void gen_lookup_tb(DisasContext *s)
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{
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@ -1300,8 +1307,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
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return;
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}
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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unallocated_encoding(s);
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}
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static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
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@ -7623,8 +7629,7 @@ static void gen_srs(DisasContext *s,
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}
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if (undef) {
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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unallocated_encoding(s);
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return;
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}
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@ -9251,8 +9256,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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break;
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default:
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illegal_op:
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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unallocated_encoding(s);
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break;
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}
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}
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@ -10940,8 +10944,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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}
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return;
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illegal_op:
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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unallocated_encoding(s);
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}
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static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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@ -11764,8 +11767,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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return;
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illegal_op:
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undef:
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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unallocated_encoding(s);
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}
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static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
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@ -99,6 +99,8 @@ typedef struct DisasCompare {
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bool value_global;
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} DisasCompare;
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void unallocated_encoding(DisasContext *s);
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/* Share the TCG temporaries common between 32 and 64 bit modes. */
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extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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extern TCGv_i64 cpu_exclusive_addr;
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