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Machine queue + QOM fixes and cleanups

Browse Source 
Bug fix:
 * numa: hmat: fix cache size check (Igor Mammedov)
 
 QOM fixes and cleanups:
 * Move QOM macros and typedefs to header files
 * Use TYPE_* constants on TypeInfo structs
 * Rename QOM type checking macros for consistency
 * Rename enum values and typedefs that conflict with QOM
   type checking amcros
 * Fix typos on QOM type checking macros
 * Delete unused QOM type checking macros that use
   non-existing typedefs
 * hvf: Add missing include
 * xen-legacy-backend: Add missing typedef XenLegacyDevice
 -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCAAyFiEEWjIv1avE09usz9GqKAeTb5hNxaYFAl9IB2UUHGVoYWJrb3N0
 QHJlZGhhdC5jb20ACgkQKAeTb5hNxaaLcA//RRqE3DOpAqUSDnaPHAVy7UDyjUwN
 1uytGKafNIBytuRmMxK76y2kez/URFxyisdWY91I7KF58S+2unggzSQF59AFt/4W
 VqSLnZxLy22xKaUBQq14VJIa4CxSOg+FfJHhLsBt2gRxbuRbvnScYcFnmZW1b/AB
 hfuibtj5m22/dMKpKquUV0xmC9JAAJqDAzwz88WA2Ybi8wqGc/6tnCQHfVG/4fsF
 TGcIn+0UzfsQlYQ+RmJYaA8FPKOjsjbHMixw3j0MfTTVLMLlqQWJaTreIvipXvC2
 Fo5S2aFBTcsoG5WIT49wbLCL2UbwiHULOC665qBy6bun/EJhhTYe4dq0zM5oTZp/
 LOT6U9BZxdLKQv53HfLDq0fWEKp05/6HZnTcwX6fG8Fi1c06aD7fQgOlwva+3sI6
 F/CuoNrbnZrwtVxi2v3lrGaUrggLZbEs33v5kieeYyszhE+gupDO5nG6zboSM0pf
 UBKHCr/5oMb8U0wEchY7/cDcZtuiMGoFNhsInE41edyA7Ss8OY+R85HQaltMrMJr
 dGnuAMEBOIOaFrJGrK5rwfBqhC4Qv4Ditrj4pJA+GAXNy3buW/TsBFJh1Pm9iiZR
 WwQHjj6kQdFJm+QgmPace3qA1+Pc8JzS44QfFO4JEkHb+/px+4icNSbcsqOxtlY2
 GdJV9NuE94Mf3W0=
 =lK8z
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

Machine queue + QOM fixes and cleanups

Bug fix:
* numa: hmat: fix cache size check (Igor Mammedov)

QOM fixes and cleanups:
* Move QOM macros and typedefs to header files
* Use TYPE_* constants on TypeInfo structs
* Rename QOM type checking macros for consistency
* Rename enum values and typedefs that conflict with QOM
  type checking amcros
* Fix typos on QOM type checking macros
* Delete unused QOM type checking macros that use
  non-existing typedefs
* hvf: Add missing include
* xen-legacy-backend: Add missing typedef XenLegacyDevice

# gpg: Signature made Thu 27 Aug 2020 20:20:05 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request: (53 commits)
  dc390: Use TYPE_DC390_DEVICE constant
  ppce500: Use TYPE_PPC_E500_PCI_BRIDGE constant
  tosa: Use TYPE_TOSA_MISC_GPIO constant
  xlnx-zcu102: Use TYPE_ZCU102_MACHINE constant
  sclpconsole: Use TYPE_* constants
  amd_iommu: Use TYPE_AMD_IOMMU_PCI constant
  nios2_iic: Use TYPE_ALTERA_IIC constant
  etsec: Use TYPE_ETSEC_COMMON constant
  migration: Rename class type checking macros
  swim: Rename struct SWIM to Swim
  s390-virtio-ccw: Rename S390_MACHINE_CLASS macro
  nubus: Rename class type checking macros
  vfio/pci: Move QOM macros to header
  kvm: Move QOM macros to kvm.h
  mptsas: Move QOM macros to header
  pxa2xx: Move QOM macros to header
  rocker: Move QOM macros to header
  auxbus: Move QOM macros to header
  piix: Move QOM macros to header
  virtio-serial-bus: Move QOM macros to header
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-08-28 11:05:08 +01:00
commit 3e39dac035
90 changed files with 621 additions and 621 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
block/throttle-groups.c
View File

@ -63,7 +63,7 @@ static void timer_cb(ThrottleGroupMember *tgm, bool is_write);
* access some other ThrottleGroupMember's timers only after verifying that
* that ThrottleGroupMember has throttled requests in the queue.
*/
typedef struct ThrottleGroup {
struct ThrottleGroup {
Object parent_obj;
/* refuse individual property change if initialization is complete */
@ -79,7 +79,7 @@ typedef struct ThrottleGroup {
/* This field is protected by the global QEMU mutex */
QTAILQ_ENTRY(ThrottleGroup) list;
} ThrottleGroup;
};
/* This is protected by the global QEMU mutex */
static QTAILQ_HEAD(, ThrottleGroup) throttle_groups =

124
hw/arm/allwinner-h3.c
View File

@ -35,37 +35,37 @@
/* Memory map */
const hwaddr allwinner_h3_memmap[] = {
[AW_H3_SRAM_A1] = 0x00000000,
[AW_H3_SRAM_A2] = 0x00044000,
[AW_H3_SRAM_C] = 0x00010000,
[AW_H3_SYSCTRL] = 0x01c00000,
[AW_H3_MMC0] = 0x01c0f000,
[AW_H3_SID] = 0x01c14000,
[AW_H3_EHCI0] = 0x01c1a000,
[AW_H3_OHCI0] = 0x01c1a400,
[AW_H3_EHCI1] = 0x01c1b000,
[AW_H3_OHCI1] = 0x01c1b400,
[AW_H3_EHCI2] = 0x01c1c000,
[AW_H3_OHCI2] = 0x01c1c400,
[AW_H3_EHCI3] = 0x01c1d000,
[AW_H3_OHCI3] = 0x01c1d400,
[AW_H3_CCU] = 0x01c20000,
[AW_H3_PIT] = 0x01c20c00,
[AW_H3_UART0] = 0x01c28000,
[AW_H3_UART1] = 0x01c28400,
[AW_H3_UART2] = 0x01c28800,
[AW_H3_UART3] = 0x01c28c00,
[AW_H3_EMAC] = 0x01c30000,
[AW_H3_DRAMCOM] = 0x01c62000,
[AW_H3_DRAMCTL] = 0x01c63000,
[AW_H3_DRAMPHY] = 0x01c65000,
[AW_H3_GIC_DIST] = 0x01c81000,
[AW_H3_GIC_CPU] = 0x01c82000,
[AW_H3_GIC_HYP] = 0x01c84000,
[AW_H3_GIC_VCPU] = 0x01c86000,
[AW_H3_RTC] = 0x01f00000,
[AW_H3_CPUCFG] = 0x01f01c00,
[AW_H3_SDRAM] = 0x40000000
[AW_H3_DEV_SRAM_A1] = 0x00000000,
[AW_H3_DEV_SRAM_A2] = 0x00044000,
[AW_H3_DEV_SRAM_C] = 0x00010000,
[AW_H3_DEV_SYSCTRL] = 0x01c00000,
[AW_H3_DEV_MMC0] = 0x01c0f000,
[AW_H3_DEV_SID] = 0x01c14000,
[AW_H3_DEV_EHCI0] = 0x01c1a000,
[AW_H3_DEV_OHCI0] = 0x01c1a400,
[AW_H3_DEV_EHCI1] = 0x01c1b000,
[AW_H3_DEV_OHCI1] = 0x01c1b400,
[AW_H3_DEV_EHCI2] = 0x01c1c000,
[AW_H3_DEV_OHCI2] = 0x01c1c400,
[AW_H3_DEV_EHCI3] = 0x01c1d000,
[AW_H3_DEV_OHCI3] = 0x01c1d400,
[AW_H3_DEV_CCU] = 0x01c20000,
[AW_H3_DEV_PIT] = 0x01c20c00,
[AW_H3_DEV_UART0] = 0x01c28000,
[AW_H3_DEV_UART1] = 0x01c28400,
[AW_H3_DEV_UART2] = 0x01c28800,
[AW_H3_DEV_UART3] = 0x01c28c00,
[AW_H3_DEV_EMAC] = 0x01c30000,
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
[AW_H3_DEV_DRAMPHY] = 0x01c65000,
[AW_H3_DEV_GIC_DIST] = 0x01c81000,
[AW_H3_DEV_GIC_CPU] = 0x01c82000,
[AW_H3_DEV_GIC_HYP] = 0x01c84000,
[AW_H3_DEV_GIC_VCPU] = 0x01c86000,
[AW_H3_DEV_RTC] = 0x01f00000,
[AW_H3_DEV_CPUCFG] = 0x01f01c00,
[AW_H3_DEV_SDRAM] = 0x40000000
};
/* List of unimplemented devices */
@ -183,7 +183,7 @@ void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
}
rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
rom_size, s->memmap[AW_H3_SRAM_A1],
rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
NULL, NULL, NULL, NULL, false);
}
@ -262,10 +262,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);
/*
* Wire the outputs from each CPU's generic timer and the GICv3
@ -312,7 +312,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
/* Timer */
sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
@ -325,32 +325,32 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
32 * KiB, &error_abort);
memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
44 * KiB, &error_abort);
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
&s->sram_a1);
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
&s->sram_a2);
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
&s->sram_c);
/* Clock Control Unit */
sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);
/* System Control */
sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);
/* CPU Configuration */
sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);
/* Security Identifier */
sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
/* SD/MMC */
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
@ -364,63 +364,63 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI0));
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI1));
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI2));
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI3));
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI0));
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI1));
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI2));
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI3));
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
/* UART1 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
/* UART2 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
/* UART3 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
/* DRAMC */
sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);
/* RTC */
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {

24
hw/arm/armsse.c
View File

@ -167,7 +167,7 @@ static void irq_status_forwarder(void *opaque, int n, int level)
static void nsccfg_handler(void *opaque, int n, int level)
{
ARMSSE *s = ARMSSE(opaque);
ARMSSE *s = ARM_SSE(opaque);
s->nsccfg = level;
}
@ -233,8 +233,8 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
static void armsse_init(Object *obj)
{
ARMSSE *s = ARMSSE(obj);
ARMSSEClass *asc = ARMSSE_GET_CLASS(obj);
ARMSSE *s = ARM_SSE(obj);
ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj);
const ARMSSEInfo *info = asc->info;
int i;
@ -391,7 +391,7 @@ static void armsse_exp_irq(void *opaque, int n, int level)
static void armsse_mpcexp_status(void *opaque, int n, int level)
{
ARMSSE *s = ARMSSE(opaque);
ARMSSE *s = ARM_SSE(opaque);
qemu_set_irq(s->mpcexp_status_in[n], level);
}
@ -401,7 +401,7 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno)
* Return a qemu_irq which can be used to signal IRQ n to
* all CPUs in the SSE.
*/
ARMSSEClass *asc = ARMSSE_GET_CLASS(s);
ARMSSEClass *asc = ARM_SSE_GET_CLASS(s);
const ARMSSEInfo *info = asc->info;
assert(irq_is_common[irqno]);
@ -428,8 +428,8 @@ static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr)
static void armsse_realize(DeviceState *dev, Error **errp)
{
ARMSSE *s = ARMSSE(dev);
ARMSSEClass *asc = ARMSSE_GET_CLASS(dev);
ARMSSE *s = ARM_SSE(dev);
ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev);
const ARMSSEInfo *info = asc->info;
int i;
MemoryRegion *mr;
@ -1114,7 +1114,7 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
* of the address bits. The NSC attribute is guest-adjustable via the
* NSCCFG register in the security controller.
*/
ARMSSE *s = ARMSSE(ii);
ARMSSE *s = ARM_SSE(ii);
int region = extract32(address, 28, 4);
*ns = !(region & 1);
@ -1136,7 +1136,7 @@ static const VMStateDescription armsse_vmstate = {
static void armsse_reset(DeviceState *dev)
{
ARMSSE *s = ARMSSE(dev);
ARMSSE *s = ARM_SSE(dev);
s->nsccfg = 0;
}
@ -1145,7 +1145,7 @@ static void armsse_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass);
ARMSSEClass *asc = ARMSSE_CLASS(klass);
ARMSSEClass *asc = ARM_SSE_CLASS(klass);
const ARMSSEInfo *info = data;
dc->realize = armsse_realize;
@ -1157,7 +1157,7 @@ static void armsse_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo armsse_info = {
.name = TYPE_ARMSSE,
.name = TYPE_ARM_SSE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMSSE),
.instance_init = armsse_init,
@ -1177,7 +1177,7 @@ static void armsse_register_types(void)
for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) {
TypeInfo ti = {
.name = armsse_variants[i].name,
.parent = TYPE_ARMSSE,
.parent = TYPE_ARM_SSE,
.class_init = armsse_class_init,
.class_data = (void *)&armsse_variants[i],
};

4
hw/arm/aspeed.c
View File

@ -309,7 +309,7 @@ static void aspeed_machine_init(MachineState *machine)
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
memory_region_add_subregion(get_system_memory(),
sc->memmap[ASPEED_SDRAM],
sc->memmap[ASPEED_DEV_SDRAM],
&bmc->ram_container);
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
@ -360,7 +360,7 @@ static void aspeed_machine_init(MachineState *machine)
}
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
aspeed_board_binfo.nb_cpus = sc->num_cpus;
if (amc->i2c_init) {

208
hw/arm/aspeed_ast2600.c
View File

@ -24,43 +24,43 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_SRAM] = 0x10000000,
[ASPEED_DEV_SRAM] = 0x10000000,
/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
[ASPEED_IOMEM] = 0x1E600000,
[ASPEED_PWM] = 0x1E610000,
[ASPEED_FMC] = 0x1E620000,
[ASPEED_SPI1] = 0x1E630000,
[ASPEED_SPI2] = 0x1E641000,
[ASPEED_EHCI1] = 0x1E6A1000,
[ASPEED_EHCI2] = 0x1E6A3000,
[ASPEED_MII1] = 0x1E650000,
[ASPEED_MII2] = 0x1E650008,
[ASPEED_MII3] = 0x1E650010,
[ASPEED_MII4] = 0x1E650018,
[ASPEED_ETH1] = 0x1E660000,
[ASPEED_ETH3] = 0x1E670000,
[ASPEED_ETH2] = 0x1E680000,
[ASPEED_ETH4] = 0x1E690000,
[ASPEED_VIC] = 0x1E6C0000,
[ASPEED_SDMC] = 0x1E6E0000,
[ASPEED_SCU] = 0x1E6E2000,
[ASPEED_XDMA] = 0x1E6E7000,
[ASPEED_ADC] = 0x1E6E9000,
[ASPEED_VIDEO] = 0x1E700000,
[ASPEED_SDHCI] = 0x1E740000,
[ASPEED_EMMC] = 0x1E750000,
[ASPEED_GPIO] = 0x1E780000,
[ASPEED_GPIO_1_8V] = 0x1E780800,
[ASPEED_RTC] = 0x1E781000,
[ASPEED_TIMER1] = 0x1E782000,
[ASPEED_WDT] = 0x1E785000,
[ASPEED_LPC] = 0x1E789000,
[ASPEED_IBT] = 0x1E789140,
[ASPEED_I2C] = 0x1E78A000,
[ASPEED_UART1] = 0x1E783000,
[ASPEED_UART5] = 0x1E784000,
[ASPEED_VUART] = 0x1E787000,
[ASPEED_SDRAM] = 0x80000000,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_PWM] = 0x1E610000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
[ASPEED_DEV_SPI2] = 0x1E641000,
[ASPEED_DEV_EHCI1] = 0x1E6A1000,
[ASPEED_DEV_EHCI2] = 0x1E6A3000,
[ASPEED_DEV_MII1] = 0x1E650000,
[ASPEED_DEV_MII2] = 0x1E650008,
[ASPEED_DEV_MII3] = 0x1E650010,
[ASPEED_DEV_MII4] = 0x1E650018,
[ASPEED_DEV_ETH1] = 0x1E660000,
[ASPEED_DEV_ETH3] = 0x1E670000,
[ASPEED_DEV_ETH2] = 0x1E680000,
[ASPEED_DEV_ETH4] = 0x1E690000,
[ASPEED_DEV_VIC] = 0x1E6C0000,
[ASPEED_DEV_SDMC] = 0x1E6E0000,
[ASPEED_DEV_SCU] = 0x1E6E2000,
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_EMMC] = 0x1E750000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
[ASPEED_DEV_RTC] = 0x1E781000,
[ASPEED_DEV_TIMER1] = 0x1E782000,
[ASPEED_DEV_WDT] = 0x1E785000,
[ASPEED_DEV_LPC] = 0x1E789000,
[ASPEED_DEV_IBT] = 0x1E789140,
[ASPEED_DEV_I2C] = 0x1E78A000,
[ASPEED_DEV_UART1] = 0x1E783000,
[ASPEED_DEV_UART5] = 0x1E784000,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_SDRAM] = 0x80000000,
};
#define ASPEED_A7MPCORE_ADDR 0x40460000
@ -69,41 +69,41 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_UART1] = 47,
[ASPEED_UART2] = 48,
[ASPEED_UART3] = 49,
[ASPEED_UART4] = 50,
[ASPEED_UART5] = 8,
[ASPEED_VUART] = 8,
[ASPEED_FMC] = 39,
[ASPEED_SDMC] = 0,
[ASPEED_SCU] = 12,
[ASPEED_ADC] = 78,
[ASPEED_XDMA] = 6,
[ASPEED_SDHCI] = 43,
[ASPEED_EHCI1] = 5,
[ASPEED_EHCI2] = 9,
[ASPEED_EMMC] = 15,
[ASPEED_GPIO] = 40,
[ASPEED_GPIO_1_8V] = 11,
[ASPEED_RTC] = 13,
[ASPEED_TIMER1] = 16,
[ASPEED_TIMER2] = 17,
[ASPEED_TIMER3] = 18,
[ASPEED_TIMER4] = 19,
[ASPEED_TIMER5] = 20,
[ASPEED_TIMER6] = 21,
[ASPEED_TIMER7] = 22,
[ASPEED_TIMER8] = 23,
[ASPEED_WDT] = 24,
[ASPEED_PWM] = 44,
[ASPEED_LPC] = 35,
[ASPEED_IBT] = 35, /* LPC */
[ASPEED_I2C] = 110, /* 110 -> 125 */
[ASPEED_ETH1] = 2,
[ASPEED_ETH2] = 3,
[ASPEED_ETH3] = 32,
[ASPEED_ETH4] = 33,
[ASPEED_DEV_UART1] = 47,
[ASPEED_DEV_UART2] = 48,
[ASPEED_DEV_UART3] = 49,
[ASPEED_DEV_UART4] = 50,
[ASPEED_DEV_UART5] = 8,
[ASPEED_DEV_VUART] = 8,
[ASPEED_DEV_FMC] = 39,
[ASPEED_DEV_SDMC] = 0,
[ASPEED_DEV_SCU] = 12,
[ASPEED_DEV_ADC] = 78,
[ASPEED_DEV_XDMA] = 6,
[ASPEED_DEV_SDHCI] = 43,
[ASPEED_DEV_EHCI1] = 5,
[ASPEED_DEV_EHCI2] = 9,
[ASPEED_DEV_EMMC] = 15,
[ASPEED_DEV_GPIO] = 40,
[ASPEED_DEV_GPIO_1_8V] = 11,
[ASPEED_DEV_RTC] = 13,
[ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_TIMER2] = 17,
[ASPEED_DEV_TIMER3] = 18,
[ASPEED_DEV_TIMER4] = 19,
[ASPEED_DEV_TIMER5] = 20,
[ASPEED_DEV_TIMER6] = 21,
[ASPEED_DEV_TIMER7] = 22,
[ASPEED_DEV_TIMER8] = 23,
[ASPEED_DEV_WDT] = 24,
[ASPEED_DEV_PWM] = 44,
[ASPEED_DEV_LPC] = 35,
[ASPEED_DEV_IBT] = 35, /* LPC */
[ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
[ASPEED_DEV_ETH1] = 2,
[ASPEED_DEV_ETH2] = 3,
[ASPEED_DEV_ETH3] = 32,
[ASPEED_DEV_ETH4] = 33,
};
@ -232,11 +232,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
qemu_irq irq;
/* IO space */
create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM],
ASPEED_SOC_IOMEM_SIZE);
/* Video engine stub */
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO],
0x1000);
/* CPU */
@ -295,21 +295,21 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(get_system_memory(),
sc->memmap[ASPEED_SRAM], &s->sram);
sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
/* RTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_RTC));
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
@ -318,16 +318,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_TIMER1]);
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hd(0)) {
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_DEV_UART5);
serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
}
@ -337,10 +337,10 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
sc->irqmap[ASPEED_I2C] + i);
sc->irqmap[ASPEED_DEV_I2C] + i);
/*
* The AST2600 SoC has one IRQ per I2C bus. Skip the common
* IRQ (AST2400 and AST2500) and connect all bussses.
@ -352,17 +352,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
&error_abort);
if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base",
sc->memmap[ASPEED_SDRAM], errp)) {
sc->memmap[ASPEED_DEV_SDRAM], errp)) {
return;
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
s->fmc.ctrl->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_FMC));
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
/* SPI */
for (i = 0; i < sc->spis_num; i++) {
@ -373,7 +373,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
sc->memmap[ASPEED_SPI1 + i]);
sc->memmap[ASPEED_DEV_SPI1 + i]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
s->spi[i].ctrl->flash_window_base);
}
@ -384,16 +384,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_EHCI1 + i]);
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
}
/* SDMC - SDRAM Memory Controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]);
/* Watch dog */
for (i = 0; i < sc->wdts_num; i++) {
@ -405,7 +405,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
sc->memmap[ASPEED_WDT] + i * awc->offset);
sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
}
/* Net */
@ -416,9 +416,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_ETH1 + i]);
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
object_property_set_link(OBJECT(&s->mii[i]), "nic",
OBJECT(&s->ftgmac100[i]), &error_abort);
@ -427,7 +427,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
sc->memmap[ASPEED_MII1 + i]);
sc->memmap[ASPEED_DEV_MII1 + i]);
}
/* XDMA */
@ -435,42 +435,42 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
sc->memmap[ASPEED_XDMA]);
sc->memmap[ASPEED_DEV_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
aspeed_soc_get_irq(s, ASPEED_XDMA));
aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_GPIO));
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
sc->memmap[ASPEED_GPIO_1_8V]);
sc->memmap[ASPEED_DEV_GPIO_1_8V]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
/* SDHCI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_SDHCI]);
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_SDHCI));
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
/* eMMC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
aspeed_soc_get_irq(s, ASPEED_EMMC));
aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
}
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)

228
hw/arm/aspeed_soc.c
View File

@ -27,97 +27,97 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_IOMEM] = 0x1E600000,
[ASPEED_FMC] = 0x1E620000,
[ASPEED_SPI1] = 0x1E630000,
[ASPEED_EHCI1] = 0x1E6A1000,
[ASPEED_VIC] = 0x1E6C0000,
[ASPEED_SDMC] = 0x1E6E0000,
[ASPEED_SCU] = 0x1E6E2000,
[ASPEED_XDMA] = 0x1E6E7000,
[ASPEED_VIDEO] = 0x1E700000,
[ASPEED_ADC] = 0x1E6E9000,
[ASPEED_SRAM] = 0x1E720000,
[ASPEED_SDHCI] = 0x1E740000,
[ASPEED_GPIO] = 0x1E780000,
[ASPEED_RTC] = 0x1E781000,
[ASPEED_TIMER1] = 0x1E782000,
[ASPEED_WDT] = 0x1E785000,
[ASPEED_PWM] = 0x1E786000,
[ASPEED_LPC] = 0x1E789000,
[ASPEED_IBT] = 0x1E789140,
[ASPEED_I2C] = 0x1E78A000,
[ASPEED_ETH1] = 0x1E660000,
[ASPEED_ETH2] = 0x1E680000,
[ASPEED_UART1] = 0x1E783000,
[ASPEED_UART5] = 0x1E784000,
[ASPEED_VUART] = 0x1E787000,
[ASPEED_SDRAM] = 0x40000000,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
[ASPEED_DEV_EHCI1] = 0x1E6A1000,
[ASPEED_DEV_VIC] = 0x1E6C0000,
[ASPEED_DEV_SDMC] = 0x1E6E0000,
[ASPEED_DEV_SCU] = 0x1E6E2000,
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_SRAM] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
[ASPEED_DEV_TIMER1] = 0x1E782000,
[ASPEED_DEV_WDT] = 0x1E785000,
[ASPEED_DEV_PWM] = 0x1E786000,
[ASPEED_DEV_LPC] = 0x1E789000,
[ASPEED_DEV_IBT] = 0x1E789140,
[ASPEED_DEV_I2C] = 0x1E78A000,
[ASPEED_DEV_ETH1] = 0x1E660000,
[ASPEED_DEV_ETH2] = 0x1E680000,
[ASPEED_DEV_UART1] = 0x1E783000,
[ASPEED_DEV_UART5] = 0x1E784000,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_SDRAM] = 0x40000000,
};
static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_IOMEM] = 0x1E600000,
[ASPEED_FMC] = 0x1E620000,
[ASPEED_SPI1] = 0x1E630000,
[ASPEED_SPI2] = 0x1E631000,
[ASPEED_EHCI1] = 0x1E6A1000,
[ASPEED_EHCI2] = 0x1E6A3000,
[ASPEED_VIC] = 0x1E6C0000,
[ASPEED_SDMC] = 0x1E6E0000,
[ASPEED_SCU] = 0x1E6E2000,
[ASPEED_XDMA] = 0x1E6E7000,
[ASPEED_ADC] = 0x1E6E9000,
[ASPEED_VIDEO] = 0x1E700000,
[ASPEED_SRAM] = 0x1E720000,
[ASPEED_SDHCI] = 0x1E740000,
[ASPEED_GPIO] = 0x1E780000,
[ASPEED_RTC] = 0x1E781000,
[ASPEED_TIMER1] = 0x1E782000,
[ASPEED_WDT] = 0x1E785000,
[ASPEED_PWM] = 0x1E786000,
[ASPEED_LPC] = 0x1E789000,
[ASPEED_IBT] = 0x1E789140,
[ASPEED_I2C] = 0x1E78A000,
[ASPEED_ETH1] = 0x1E660000,
[ASPEED_ETH2] = 0x1E680000,
[ASPEED_UART1] = 0x1E783000,
[ASPEED_UART5] = 0x1E784000,
[ASPEED_VUART] = 0x1E787000,
[ASPEED_SDRAM] = 0x80000000,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
[ASPEED_DEV_SPI2] = 0x1E631000,
[ASPEED_DEV_EHCI1] = 0x1E6A1000,
[ASPEED_DEV_EHCI2] = 0x1E6A3000,
[ASPEED_DEV_VIC] = 0x1E6C0000,
[ASPEED_DEV_SDMC] = 0x1E6E0000,
[ASPEED_DEV_SCU] = 0x1E6E2000,
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_SRAM] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
[ASPEED_DEV_TIMER1] = 0x1E782000,
[ASPEED_DEV_WDT] = 0x1E785000,
[ASPEED_DEV_PWM] = 0x1E786000,
[ASPEED_DEV_LPC] = 0x1E789000,
[ASPEED_DEV_IBT] = 0x1E789140,
[ASPEED_DEV_I2C] = 0x1E78A000,
[ASPEED_DEV_ETH1] = 0x1E660000,
[ASPEED_DEV_ETH2] = 0x1E680000,
[ASPEED_DEV_UART1] = 0x1E783000,
[ASPEED_DEV_UART5] = 0x1E784000,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_SDRAM] = 0x80000000,
};
static const int aspeed_soc_ast2400_irqmap[] = {
[ASPEED_UART1] = 9,
[ASPEED_UART2] = 32,
[ASPEED_UART3] = 33,
[ASPEED_UART4] = 34,
[ASPEED_UART5] = 10,
[ASPEED_VUART] = 8,
[ASPEED_FMC] = 19,
[ASPEED_EHCI1] = 5,
[ASPEED_EHCI2] = 13,
[ASPEED_SDMC] = 0,
[ASPEED_SCU] = 21,
[ASPEED_ADC] = 31,
[ASPEED_GPIO] = 20,
[ASPEED_RTC] = 22,
[ASPEED_TIMER1] = 16,
[ASPEED_TIMER2] = 17,
[ASPEED_TIMER3] = 18,
[ASPEED_TIMER4] = 35,
[ASPEED_TIMER5] = 36,
[ASPEED_TIMER6] = 37,
[ASPEED_TIMER7] = 38,
[ASPEED_TIMER8] = 39,
[ASPEED_WDT] = 27,
[ASPEED_PWM] = 28,
[ASPEED_LPC] = 8,
[ASPEED_IBT] = 8, /* LPC */
[ASPEED_I2C] = 12,
[ASPEED_ETH1] = 2,
[ASPEED_ETH2] = 3,
[ASPEED_XDMA] = 6,
[ASPEED_SDHCI] = 26,
[ASPEED_DEV_UART1] = 9,
[ASPEED_DEV_UART2] = 32,
[ASPEED_DEV_UART3] = 33,
[ASPEED_DEV_UART4] = 34,
[ASPEED_DEV_UART5] = 10,
[ASPEED_DEV_VUART] = 8,
[ASPEED_DEV_FMC] = 19,
[ASPEED_DEV_EHCI1] = 5,
[ASPEED_DEV_EHCI2] = 13,
[ASPEED_DEV_SDMC] = 0,
[ASPEED_DEV_SCU] = 21,
[ASPEED_DEV_ADC] = 31,
[ASPEED_DEV_GPIO] = 20,
[ASPEED_DEV_RTC] = 22,
[ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_TIMER2] = 17,
[ASPEED_DEV_TIMER3] = 18,
[ASPEED_DEV_TIMER4] = 35,
[ASPEED_DEV_TIMER5] = 36,
[ASPEED_DEV_TIMER6] = 37,
[ASPEED_DEV_TIMER7] = 38,
[ASPEED_DEV_TIMER8] = 39,
[ASPEED_DEV_WDT] = 27,
[ASPEED_DEV_PWM] = 28,
[ASPEED_DEV_LPC] = 8,
[ASPEED_DEV_IBT] = 8, /* LPC */
[ASPEED_DEV_I2C] = 12,
[ASPEED_DEV_ETH1] = 2,
[ASPEED_DEV_ETH2] = 3,
[ASPEED_DEV_XDMA] = 6,
[ASPEED_DEV_SDHCI] = 26,
};
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
@ -221,11 +221,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
/* IO space */
create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM],
ASPEED_SOC_IOMEM_SIZE);
/* Video engine stub */
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO],
0x1000);
/* CPU */
@ -243,19 +243,19 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(get_system_memory(),
sc->memmap[ASPEED_SRAM], &s->sram);
sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
/* VIC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
@ -265,9 +265,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_RTC));
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
@ -276,16 +276,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_TIMER1]);
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hd(0)) {
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_DEV_UART5);
serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
}
@ -295,25 +295,25 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
aspeed_soc_get_irq(s, ASPEED_I2C));
aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
/* FMC, The number of CS is set at the board level */
object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
&error_abort);
if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base",
sc->memmap[ASPEED_SDRAM], errp)) {
sc->memmap[ASPEED_DEV_SDRAM], errp)) {
return;
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
s->fmc.ctrl->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_FMC));
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
/* SPI */
for (i = 0; i < sc->spis_num; i++) {
@ -322,7 +322,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
sc->memmap[ASPEED_SPI1 + i]);
sc->memmap[ASPEED_DEV_SPI1 + i]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
s->spi[i].ctrl->flash_window_base);
}
@ -333,16 +333,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_EHCI1 + i]);
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
}
/* SDMC - SDRAM Memory Controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]);
/* Watch dog */
for (i = 0; i < sc->wdts_num; i++) {
@ -354,7 +354,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
sc->memmap[ASPEED_WDT] + i * awc->offset);
sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
}
/* Net */
@ -365,9 +365,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_ETH1 + i]);
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
}
/* XDMA */
@ -375,26 +375,26 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
sc->memmap[ASPEED_XDMA]);
sc->memmap[ASPEED_DEV_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
aspeed_soc_get_irq(s, ASPEED_XDMA));
aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_GPIO));
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
/* SDHCI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_SDHCI]);
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_SDHCI));
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
}
static Property aspeed_soc_properties[] = {
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,

6
hw/arm/orangepi.c
View File

@ -79,7 +79,7 @@ static void orangepi_init(MachineState *machine)
object_property_set_int(OBJECT(&h3->emac), "phy-addr", 1, &error_abort);
/* DRAMC */
object_property_set_uint(OBJECT(h3), "ram-addr", h3->memmap[AW_H3_SDRAM],
object_property_set_uint(OBJECT(h3), "ram-addr", h3->memmap[AW_H3_DEV_SDRAM],
&error_abort);
object_property_set_int(OBJECT(h3), "ram-size", machine->ram_size / MiB,
&error_abort);
@ -98,7 +98,7 @@ static void orangepi_init(MachineState *machine)
qdev_realize_and_unref(carddev, bus, &error_fatal);
/* SDRAM */
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_DEV_SDRAM],
machine->ram);
/* Load target kernel or start using BootROM */
@ -106,7 +106,7 @@ static void orangepi_init(MachineState *machine)
/* Use Boot ROM to copy data from SD card to SRAM */
allwinner_h3_bootrom_setup(h3, blk);
}
orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
orangepi_binfo.ram_size = machine->ram_size;
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
}

7
hw/arm/pxa2xx.c
View File

@ -1251,10 +1251,6 @@ typedef struct PXA2xxI2CSlaveState {
PXA2xxI2CState *host;
} PXA2xxI2CSlaveState;
#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
#define PXA2XX_I2C(obj) \
OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
struct PXA2xxI2CState {
/*< private >*/
SysBusDevice parent_obj;
@ -1787,9 +1783,6 @@ static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
}
/* PXA Fast Infra-red Communications Port */
#define TYPE_PXA2XX_FIR "pxa2xx-fir"
#define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
struct PXA2xxFIrState {
/*< private >*/
SysBusDevice parent_obj;

2
hw/arm/tosa.c
View File

@ -316,7 +316,7 @@ static const TypeInfo tosa_ssp_info = {
};
static const TypeInfo tosa_misc_gpio_info = {
.name = "tosa-misc-gpio",
.name = TYPE_TOSA_MISC_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(TosaMiscGPIOState),
.instance_init = tosa_misc_gpio_init,

2
hw/arm/xlnx-zcu102.c
View File

@ -238,7 +238,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
}
static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
.name = MACHINE_TYPE_NAME("xlnx-zcu102"),
.name = TYPE_ZCU102_MACHINE,
.parent = TYPE_MACHINE,
.class_init = xlnx_zcu102_machine_class_init,
.instance_init = xlnx_zcu102_machine_instance_init,

10
hw/block/swim.c
View File

@ -387,7 +387,7 @@ static const MemoryRegionOps swimctrl_mem_ops = {
static void sysbus_swim_reset(DeviceState *d)
{
SWIM *sys = SWIM(d);
Swim *sys = SWIM(d);
SWIMCtrl *ctrl = &sys->ctrl;
int i;
@ -408,7 +408,7 @@ static void sysbus_swim_reset(DeviceState *d)
static void sysbus_swim_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
SWIM *sbs = SWIM(obj);
Swim *sbs = SWIM(obj);
SWIMCtrl *swimctrl = &sbs->ctrl;
memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimctrl,
@ -418,7 +418,7 @@ static void sysbus_swim_init(Object *obj)
static void sysbus_swim_realize(DeviceState *dev, Error **errp)
{
SWIM *sys = SWIM(dev);
Swim *sys = SWIM(dev);
SWIMCtrl *swimctrl = &sys->ctrl;
qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev,
@ -460,7 +460,7 @@ static const VMStateDescription vmstate_sysbus_swim = {
.name = "SWIM",
.version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(ctrl, SWIM, 0, vmstate_swim, SWIMCtrl),
VMSTATE_STRUCT(ctrl, Swim, 0, vmstate_swim, SWIMCtrl),
VMSTATE_END_OF_LIST()
}
};
@ -477,7 +477,7 @@ static void sysbus_swim_class_init(ObjectClass *oc, void *data)
static const TypeInfo sysbus_swim_info = {
.name = TYPE_SWIM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SWIM),
.instance_size = sizeof(Swim),
.instance_init = sysbus_swim_init,
.class_init = sysbus_swim_class_init,
};

2
hw/char/sclpconsole-lm.c
View File

@ -355,7 +355,7 @@ static void console_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sclp_console_info = {
.name = "sclplmconsole",
.name = TYPE_SCLPLM_CONSOLE,
.parent = TYPE_SCLP_EVENT,
.instance_size = sizeof(SCLPConsoleLM),
.class_init = console_class_init,

2
hw/char/sclpconsole.c
View File

@ -271,7 +271,7 @@ static void console_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sclp_console_info = {
.name = "sclpconsole",
.name = TYPE_SCLP_CONSOLE,
.parent = TYPE_SCLP_EVENT,
.instance_size = sizeof(SCLPConsole),
.class_init = console_class_init,

4
hw/char/virtio-serial-bus.c
View File

@ -843,10 +843,6 @@ static Property virtser_props[] = {
DEFINE_PROP_END_OF_LIST()
};
#define TYPE_VIRTIO_SERIAL_BUS "virtio-serial-bus"
#define VIRTIO_SERIAL_BUS(obj) \
OBJECT_CHECK(VirtIOSerialBus, (obj), TYPE_VIRTIO_SERIAL_BUS)
static void virtser_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);

8
hw/core/numa.c
View File

@ -425,10 +425,10 @@ void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
if ((node->level > 1) &&
ms->numa_state->hmat_cache[node->node_id][node->level - 1] &&
(node->size >=
(node->size <=
ms->numa_state->hmat_cache[node->node_id][node->level - 1]->size)) {
error_setg(errp, "Invalid size=%" PRIu64 ", the size of level=%" PRIu8
" should be less than the size(%" PRIu64 ") of "
" should be larger than the size(%" PRIu64 ") of "
"level=%u", node->size, node->level,
ms->numa_state->hmat_cache[node->node_id]
[node->level - 1]->size,
@ -438,10 +438,10 @@ void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
if ((node->level < HMAT_LB_LEVELS - 1) &&
ms->numa_state->hmat_cache[node->node_id][node->level + 1] &&
(node->size <=
(node->size >=
ms->numa_state->hmat_cache[node->node_id][node->level + 1]->size)) {
error_setg(errp, "Invalid size=%" PRIu64 ", the size of level=%" PRIu8
" should be larger than the size(%" PRIu64 ") of "
" should be less than the size(%" PRIu64 ") of "
"level=%u", node->size, node->level,
ms->numa_state->hmat_cache[node->node_id]
[node->level + 1]->size,

4
hw/display/macfb.c
View File

@ -391,7 +391,7 @@ static void macfb_nubus_realize(DeviceState *dev, Error **errp)
{
NubusDevice *nd = NUBUS_DEVICE(dev);
MacfbNubusState *s = NUBUS_MACFB(dev);
MacfbNubusDeviceClass *ndc = MACFB_NUBUS_GET_CLASS(dev);
MacfbNubusDeviceClass *ndc = NUBUS_MACFB_GET_CLASS(dev);
MacfbState *ms = &s->macfb;
ndc->parent_realize(dev, errp);
@ -443,7 +443,7 @@ static void macfb_sysbus_class_init(ObjectClass *klass, void *data)
static void macfb_nubus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
MacfbNubusDeviceClass *ndc = MACFB_NUBUS_DEVICE_CLASS(klass);
MacfbNubusDeviceClass *ndc = NUBUS_MACFB_CLASS(klass);
device_class_set_parent_realize(dc, macfb_nubus_realize,
&ndc->parent_realize);

22
hw/display/pl110.c
View File

@ -42,9 +42,9 @@ enum pl110_bppmode
/* The Versatile/PB uses a slightly modified PL110 controller. */
enum pl110_version
{
PL110,
PL110_VERSATILE,
PL111
VERSION_PL110,
VERSION_PL110_VERSATILE,
VERSION_PL111
};
#define TYPE_PL110 "pl110"
@ -189,7 +189,7 @@ static void pl110_update_display(void *opaque)
else
bpp_offset = 24;
if ((s->version != PL111) && (s->bpp == BPP_16)) {
if ((s->version != VERSION_PL111) && (s->bpp == BPP_16)) {
/* The PL110's native 16 bit mode is 5551; however
* most boards with a PL110 implement an external
* mux which allows bits to be reshuffled to give
@ -372,12 +372,12 @@ static uint64_t pl110_read(void *opaque, hwaddr offset,
case 5: /* LCDLPBASE */
return s->lpbase;
case 6: /* LCDIMSC */
if (s->version != PL110) {
if (s->version != VERSION_PL110) {
return s->cr;
}
return s->int_mask;
case 7: /* LCDControl */
if (s->version != PL110) {
if (s->version != VERSION_PL110) {
return s->int_mask;
}
return s->cr;
@ -437,7 +437,7 @@ static void pl110_write(void *opaque, hwaddr offset,
s->lpbase = val;
break;
case 6: /* LCDIMSC */
if (s->version != PL110) {
if (s->version != VERSION_PL110) {
goto control;
}
imsc:
@ -445,7 +445,7 @@ static void pl110_write(void *opaque, hwaddr offset,
pl110_update(s);
break;
case 7: /* LCDControl */
if (s->version != PL110) {
if (s->version != VERSION_PL110) {
goto imsc;
}
control:
@ -513,21 +513,21 @@ static void pl110_init(Object *obj)
{
PL110State *s = PL110(obj);
s->version = PL110;
s->version = VERSION_PL110;
}
static void pl110_versatile_init(Object *obj)
{
PL110State *s = PL110(obj);
s->version = PL110_VERSATILE;
s->version = VERSION_PL110_VERSATILE;
}
static void pl111_init(Object *obj)
{
PL110State *s = PL110(obj);
s->version = PL111;
s->version = VERSION_PL111;
}
static void pl110_class_init(ObjectClass *klass, void *data)

3
hw/display/vhost-user-gpu.c
View File

@ -17,9 +17,6 @@
#include "qapi/error.h"
#include "migration/blocker.h"
#define VHOST_USER_GPU(obj) \
OBJECT_CHECK(VhostUserGPU, (obj), TYPE_VHOST_USER_GPU)
typedef enum VhostUserGpuRequest {
VHOST_USER_GPU_NONE = 0,
VHOST_USER_GPU_GET_PROTOCOL_FEATURES,

2
hw/dma/i8257.c
View File

@ -33,8 +33,6 @@
#include "qemu/log.h"
#include "trace.h"
#define I8257(obj) \
OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
/* #define DEBUG_DMA */

3
hw/hyperv/vmbus.c
View File

@ -20,9 +20,6 @@
#include "cpu.h"
#include "trace.h"
#define TYPE_VMBUS "vmbus"
#define VMBUS(obj) OBJECT_CHECK(VMBus, (obj), TYPE_VMBUS)
enum {
VMGPADL_INIT,
VMGPADL_ALIVE,

2
hw/i386/amd_iommu.c
View File

@ -1622,7 +1622,7 @@ static const TypeInfo amdvi = {
};
static const TypeInfo amdviPCI = {
.name = "AMDVI-PCI",
.name = TYPE_AMD_IOMMU_PCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(AMDVIPCIState),
.interfaces = (InterfaceInfo[]) {

3
hw/ide/ahci-allwinner.c
View File

@ -25,9 +25,6 @@
#include "trace.h"
#define ALLWINNER_AHCI(obj) \
OBJECT_CHECK(AllwinnerAHCIState, (obj), TYPE_ALLWINNER_AHCI)
#define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
#define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)

5
hw/ide/ahci_internal.h
View File

@ -332,9 +332,6 @@ struct AHCIPCIState {
AHCIState ahci;
};
#define ICH_AHCI(obj) \
OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
extern const VMStateDescription vmstate_ahci;
#define VMSTATE_AHCI(_field, _state) { \
@ -394,6 +391,4 @@ void ahci_uninit(AHCIState *s);
void ahci_reset(AHCIState *s);
#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
#endif /* HW_IDE_AHCI_INTERNAL_H */

2
hw/input/pckbd.c
View File

@ -481,8 +481,6 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
qemu_register_reset(kbd_reset, s);
}
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
struct ISAKBDState {
ISADevice parent_obj;

2
hw/intc/nios2_iic.c
View File

@ -80,7 +80,7 @@ static void altera_iic_class_init(ObjectClass *klass, void *data)
}
static TypeInfo altera_iic_info = {
.name = "altera,iic",
.name = TYPE_ALTERA_IIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AlteraIIC),
.instance_init = altera_iic_init,

4
hw/intc/s390_flic_kvm.c
View File

@ -29,12 +29,12 @@
#define FLIC_FAILED (-1UL)
#define FLIC_SAVEVM_VERSION 1
typedef struct KVMS390FLICState {
struct KVMS390FLICState{
S390FLICState parent_obj;
uint32_t fd;
bool clear_io_supported;
} KVMS390FLICState;
};
static KVMS390FLICState *s390_get_kvm_flic(S390FLICState *fs)
{

4
hw/isa/piix3.c
View File

@ -36,10 +36,6 @@
#define XEN_PIIX_NUM_PIRQS 128ULL
#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
#define PIIX3_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
#define TYPE_PIIX3_DEVICE "PIIX3"
#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"

2
hw/misc/auxbus.c
View File

@ -45,8 +45,6 @@
} \
} while (0)
#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge);

8
hw/net/e1000.c
View File

@ -151,9 +151,9 @@ typedef struct E1000BaseClass {
#define E1000(obj) \
OBJECT_CHECK(E1000State, (obj), TYPE_E1000_BASE)
#define E1000_DEVICE_CLASS(klass) \
#define E1000_CLASS(klass) \
OBJECT_CLASS_CHECK(E1000BaseClass, (klass), TYPE_E1000_BASE)
#define E1000_DEVICE_GET_CLASS(obj) \
#define E1000_GET_CLASS(obj) \
OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE)
static void
@ -365,7 +365,7 @@ e1000_autoneg_timer(void *opaque)
static void e1000_reset(void *opaque)
{
E1000State *d = opaque;
E1000BaseClass *edc = E1000_DEVICE_GET_CLASS(d);
E1000BaseClass *edc = E1000_GET_CLASS(d);
uint8_t *macaddr = d->conf.macaddr.a;
timer_del(d->autoneg_timer);
@ -1751,7 +1751,7 @@ static void e1000_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
E1000BaseClass *e = E1000_DEVICE_CLASS(klass);
E1000BaseClass *e = E1000_CLASS(klass);
const E1000Info *info = data;
k->realize = pci_e1000_realize;

2
hw/net/fsl_etsec/etsec.c
View File

@ -430,7 +430,7 @@ static void etsec_class_init(ObjectClass *klass, void *data)
}
static TypeInfo etsec_info = {
.name = "eTSEC",
.name = TYPE_ETSEC_COMMON,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(eTSEC),
.class_init = etsec_class_init,

4
hw/net/mcf_fec.c
View File

@ -32,7 +32,7 @@ do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
#define FEC_MAX_FRAME_SIZE 2032
#define FEC_MIB_SIZE 64
typedef struct {
struct mcf_fec_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -56,7 +56,7 @@ typedef struct {
uint32_t etdsr;
uint32_t emrbr;
uint32_t mib[FEC_MIB_SIZE];
} mcf_fec_state;
};
#define FEC_INT_HB 0x80000000
#define FEC_INT_BABR 0x40000000

5
hw/net/rocker/rocker.c
View File

@ -73,11 +73,6 @@ struct rocker {
QLIST_ENTRY(rocker) next;
};
#define TYPE_ROCKER "rocker"
#define ROCKER(obj) \
OBJECT_CHECK(Rocker, (obj), TYPE_ROCKER)
static QLIST_HEAD(, rocker) rockers;
Rocker *rocker_find(const char *name)

6
hw/net/rocker/rocker.h
View File

@ -66,11 +66,15 @@ static inline bool ipv6_addr_is_multicast(const Ipv6Addr *addr)
return (addr->addr32[0] & htonl(0xFF000000)) == htonl(0xFF000000);
}
typedef struct rocker Rocker;
typedef struct world World;
typedef struct desc_info DescInfo;
typedef struct desc_ring DescRing;
#define TYPE_ROCKER "rocker"
typedef struct rocker Rocker;
#define ROCKER(obj) \
OBJECT_CHECK(Rocker, (obj), TYPE_ROCKER)
Rocker *rocker_find(const char *name);
uint32_t rocker_fp_ports(Rocker *r);
int rocker_event_link_changed(Rocker *r, uint32_t pport, bool link_up);

4
hw/net/tulip.c
View File

@ -18,7 +18,7 @@
#include "trace.h"
#include "net/eth.h"
typedef struct TULIPState {
struct TULIPState {
PCIDevice dev;
MemoryRegion io;
MemoryRegion memory;
@ -44,7 +44,7 @@ typedef struct TULIPState {
uint32_t rx_status;
uint8_t filter[16][6];
} TULIPState;
};
static const VMStateDescription vmstate_pci_tulip = {
.name = "tulip",

1
hw/net/tulip.h
View File

@ -5,6 +5,7 @@
#include "net/net.h"
#define TYPE_TULIP "tulip"
typedef struct TULIPState TULIPState;
#define TULIP(obj) OBJECT_CHECK(TULIPState, (obj), TYPE_TULIP)
#define CSR(_x) ((_x) << 3)

2
hw/pci-host/ppce500.c
View File

@ -509,7 +509,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo e500_host_bridge_info = {
.name = "e500-host-bridge",
.name = TYPE_PPC_E500_PCI_BRIDGE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PPCE500PCIBridgeState),
.class_init = e500_host_bridge_class_init,

2
hw/pci-host/versatile.c
View File

@ -161,7 +161,7 @@ static const VMStateDescription pci_vpb_vmstate = {
#define TYPE_VERSATILE_PCI_HOST "versatile_pci_host"
#define PCI_VPB_HOST(obj) \
OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST)
OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCI_HOST)
typedef enum {
PCI_IMAP0 = 0x0,

4
hw/pcmcia/pxa2xx.c
View File

@ -18,10 +18,6 @@
#include "hw/pcmcia.h"
#include "hw/arm/pxa.h"
#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
#define PXA2XX_PCMCIA(obj) \
OBJECT_CHECK(PXA2xxPCMCIAState, obj, TYPE_PXA2XX_PCMCIA)
struct PXA2xxPCMCIAState {
SysBusDevice parent_obj;

84
hw/riscv/opentitan.c
View File

@ -32,25 +32,25 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} ibex_memmap[] = {
[IBEX_ROM] = { 0x00008000, 16 * KiB },
[IBEX_RAM] = { 0x10000000, 0x10000 },
[IBEX_FLASH] = { 0x20000000, 0x80000 },
[IBEX_UART] = { 0x40000000, 0x10000 },
[IBEX_GPIO] = { 0x40010000, 0x10000 },
[IBEX_SPI] = { 0x40020000, 0x10000 },
[IBEX_FLASH_CTRL] = { 0x40030000, 0x10000 },
[IBEX_PINMUX] = { 0x40070000, 0x10000 },
[IBEX_RV_TIMER] = { 0x40080000, 0x10000 },
[IBEX_PLIC] = { 0x40090000, 0x10000 },
[IBEX_PWRMGR] = { 0x400A0000, 0x10000 },
[IBEX_RSTMGR] = { 0x400B0000, 0x10000 },
[IBEX_CLKMGR] = { 0x400C0000, 0x10000 },
[IBEX_AES] = { 0x40110000, 0x10000 },
[IBEX_HMAC] = { 0x40120000, 0x10000 },
[IBEX_ALERT_HANDLER] = { 0x40130000, 0x10000 },
[IBEX_NMI_GEN] = { 0x40140000, 0x10000 },
[IBEX_USBDEV] = { 0x40150000, 0x10000 },
[IBEX_PADCTRL] = { 0x40160000, 0x10000 }
[IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
[IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
[IBEX_DEV_UART] = { 0x40000000, 0x10000 },
[IBEX_DEV_GPIO] = { 0x40010000, 0x10000 },
[IBEX_DEV_SPI] = { 0x40020000, 0x10000 },
[IBEX_DEV_FLASH_CTRL] = { 0x40030000, 0x10000 },
[IBEX_DEV_PINMUX] = { 0x40070000, 0x10000 },
[IBEX_DEV_RV_TIMER] = { 0x40080000, 0x10000 },
[IBEX_DEV_PLIC] = { 0x40090000, 0x10000 },
[IBEX_DEV_PWRMGR] = { 0x400A0000, 0x10000 },
[IBEX_DEV_RSTMGR] = { 0x400B0000, 0x10000 },
[IBEX_DEV_CLKMGR] = { 0x400C0000, 0x10000 },
[IBEX_DEV_AES] = { 0x40110000, 0x10000 },
[IBEX_DEV_HMAC] = { 0x40120000, 0x10000 },
[IBEX_DEV_ALERT_HANDLER] = { 0x40130000, 0x10000 },
[IBEX_DEV_NMI_GEN] = { 0x40140000, 0x10000 },
[IBEX_DEV_USBDEV] = { 0x40150000, 0x10000 },
[IBEX_DEV_PADCTRL] = { 0x40160000, 0x10000 }
};
static void opentitan_board_init(MachineState *machine)
@ -66,12 +66,12 @@ static void opentitan_board_init(MachineState *machine)
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
memmap[IBEX_RAM].size, &error_fatal);
memmap[IBEX_DEV_RAM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
memmap[IBEX_RAM].base, main_mem);
memmap[IBEX_DEV_RAM].base, main_mem);
if (machine->firmware) {
riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
}
if (machine->kernel_filename) {
@ -115,28 +115,28 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
memmap[IBEX_ROM].size, &error_fatal);
memmap[IBEX_DEV_ROM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
memmap[IBEX_ROM].base, &s->rom);
memmap[IBEX_DEV_ROM].base, &s->rom);
/* Flash memory */
memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
memmap[IBEX_FLASH].size, &error_fatal);
memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,
memmap[IBEX_DEV_FLASH].size, &error_fatal);
memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
&s->flash_mem);
/* PLIC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
/* UART */
qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_UART].base);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART_TX_WATERMARK_IRQ));
@ -151,33 +151,33 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
IBEX_UART_RX_OVERFLOW_IRQ));
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi",
memmap[IBEX_SPI].base, memmap[IBEX_SPI].size);
memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size);
memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size);
memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
memmap[IBEX_PWRMGR].base, memmap[IBEX_PWRMGR].size);
memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
memmap[IBEX_RSTMGR].base, memmap[IBEX_RSTMGR].size);
memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
memmap[IBEX_CLKMGR].base, memmap[IBEX_CLKMGR].size);
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.aes",
memmap[IBEX_AES].base, memmap[IBEX_AES].size);
memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);
memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);
memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size);
memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
memmap[IBEX_NMI_GEN].base, memmap[IBEX_NMI_GEN].size);
memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size);
memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
}
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)

14
hw/s390x/s390-virtio-ccw.c
View File

@ -596,7 +596,7 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
S390CcwMachineClass *s390mc = S390_MACHINE_CLASS(mc);
S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc);
s390mc->ri_allowed = true;
s390mc->cpu_model_allowed = true;
@ -677,7 +677,7 @@ static S390CcwMachineClass *get_machine_class(void)
* be called for the 'none' machine. The properties will
* have their after-initialization values.
*/
current_mc = S390_MACHINE_CLASS(
current_mc = S390_CCW_MACHINE_CLASS(
object_class_by_name(TYPE_S390_CCW_MACHINE));
}
return current_mc;
@ -786,7 +786,7 @@ bool css_migration_enabled(void)
static void ccw_machine_##suffix##_instance_init(Object *obj) \
{ \
MachineState *machine = MACHINE(obj); \
current_mc = S390_MACHINE_CLASS(MACHINE_GET_CLASS(machine)); \
current_mc = S390_CCW_MACHINE_CLASS(MACHINE_GET_CLASS(machine)); \
ccw_machine_##suffix##_instance_options(machine); \
} \
static const TypeInfo ccw_machine_##suffix##_info = { \
@ -898,7 +898,7 @@ static void ccw_machine_3_0_instance_options(MachineState *machine)
static void ccw_machine_3_0_class_options(MachineClass *mc)
{
S390CcwMachineClass *s390mc = S390_MACHINE_CLASS(mc);
S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc);
s390mc->hpage_1m_allowed = false;
ccw_machine_3_1_class_options(mc);
@ -965,7 +965,7 @@ static void ccw_machine_2_9_instance_options(MachineState *machine)
static void ccw_machine_2_9_class_options(MachineClass *mc)
{
S390CcwMachineClass *s390mc = S390_MACHINE_CLASS(mc);
S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc);
static GlobalProperty compat[] = {
{ TYPE_S390_STATTRIB, "migration-enabled", "off", },
};
@ -1001,7 +1001,7 @@ static void ccw_machine_2_7_instance_options(MachineState *machine)
static void ccw_machine_2_7_class_options(MachineClass *mc)
{
S390CcwMachineClass *s390mc = S390_MACHINE_CLASS(mc);
S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc);
s390mc->cpu_model_allowed = false;
ccw_machine_2_8_class_options(mc);
@ -1016,7 +1016,7 @@ static void ccw_machine_2_6_instance_options(MachineState *machine)
static void ccw_machine_2_6_class_options(MachineClass *mc)
{
S390CcwMachineClass *s390mc = S390_MACHINE_CLASS(mc);
S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc);
static GlobalProperty compat[] = {
{ TYPE_S390_IPL, "iplbext_migration", "off", },
{ TYPE_VIRTUAL_CSS_BRIDGE, "css_dev_path", "off", },

4
hw/s390x/virtio-ccw.h
View File

@ -65,9 +65,9 @@ typedef struct VirtioBusClass VirtioCcwBusClass;
#define TYPE_VIRTIO_CCW_BUS "virtio-ccw-bus"
#define VIRTIO_CCW_BUS(obj) \
OBJECT_CHECK(VirtioCcwBus, (obj), TYPE_VIRTIO_CCW_BUS)
OBJECT_CHECK(VirtioCcwBusState, (obj), TYPE_VIRTIO_CCW_BUS)
#define VIRTIO_CCW_BUS_GET_CLASS(obj) \
OBJECT_CHECK(VirtioCcwBusState, (obj), TYPE_VIRTIO_CCW_BUS)
OBJECT_GET_CLASS(VirtioCcwBusClass, (obj), TYPE_VIRTIO_CCW_BUS)
#define VIRTIO_CCW_BUS_CLASS(klass) \
OBJECT_CLASS_CHECK(VirtioCcwBusClass, klass, TYPE_VIRTIO_CCW_BUS)

2
hw/scsi/esp-pci.c
View File

@ -521,7 +521,7 @@ static void dc390_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo dc390_info = {
.name = "dc390",
.name = TYPE_DC390_DEVICE,
.parent = TYPE_AM53C974_DEVICE,
.instance_size = sizeof(DC390State),
.class_init = dc390_class_init,

12
hw/scsi/megasas.c
View File

@ -134,9 +134,9 @@ typedef struct MegasasBaseClass {
#define MEGASAS(obj) \
OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
#define MEGASAS_DEVICE_CLASS(oc) \
#define MEGASAS_CLASS(oc) \
OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
#define MEGASAS_DEVICE_GET_CLASS(oc) \
#define MEGASAS_GET_CLASS(oc) \
OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
@ -733,7 +733,7 @@ static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
{
PCIDevice *pci_dev = PCI_DEVICE(s);
PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
struct mfi_ctrl_info info;
size_t dcmd_size = sizeof(info);
BusChild *kid;
@ -1999,7 +1999,7 @@ static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
{
MegasasState *s = opaque;
PCIDevice *pci_dev = PCI_DEVICE(s);
MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
uint32_t retval = 0;
switch (addr) {
@ -2322,7 +2322,7 @@ static const struct SCSIBusInfo megasas_scsi_info = {
static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
{
MegasasState *s = MEGASAS(dev);
MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
MegasasBaseClass *b = MEGASAS_GET_CLASS(s);
uint8_t *pci_conf;
int i, bar_type;
Error *err = NULL;
@ -2506,7 +2506,7 @@ static void megasas_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
MegasasBaseClass *e = MEGASAS_CLASS(oc);
const MegasasInfo *info = data;
pc->realize = megasas_scsi_realize;

5
hw/scsi/mptsas.c
View File

@ -42,11 +42,6 @@
#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
#define TYPE_MPTSAS1068 "mptsas1068"
#define MPT_SAS(obj) \
OBJECT_CHECK(MPTSASState, (obj), TYPE_MPTSAS1068)
#define MPTSAS1068_PRODUCT_ID \
(MPI_FW_HEADER_PID_FAMILY_1068_SAS | \
MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \

6
hw/scsi/mptsas.h
View File

@ -11,9 +11,13 @@
#define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22
typedef struct MPTSASState MPTSASState;
typedef struct MPTSASRequest MPTSASRequest;
#define TYPE_MPTSAS1068 "mptsas1068"
typedef struct MPTSASState MPTSASState;
#define MPT_SAS(obj) \
OBJECT_CHECK(MPTSASState, (obj), TYPE_MPTSAS1068)
enum {
DOORBELL_NONE,
DOORBELL_WRITE,

8
hw/scsi/vmw_pvscsi.c
View File

@ -64,9 +64,9 @@ typedef struct PVSCSIClass {
#define TYPE_PVSCSI "pvscsi"
#define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
#define PVSCSI_DEVICE_CLASS(klass) \
#define PVSCSI_CLASS(klass) \
OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
#define PVSCSI_DEVICE_GET_CLASS(obj) \
#define PVSCSI_GET_CLASS(obj) \
OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
/* Compatibility flags for migration */
@ -1265,7 +1265,7 @@ static Property pvscsi_properties[] = {
static void pvscsi_realize(DeviceState *qdev, Error **errp)
{
PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev);
PCIDevice *pci_dev = PCI_DEVICE(qdev);
PVSCSIState *s = PVSCSI(qdev);
@ -1280,7 +1280,7 @@ static void pvscsi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
PVSCSIClass *pvs_k = PVSCSI_CLASS(klass);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
k->realize = pvscsi_realizefn;

3
hw/sd/pxa2xx_mmci.c
View File

@ -22,9 +22,6 @@
#include "qemu/module.h"
#include "trace.h"
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
#define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)

8
hw/usb/hcd-dwc2.c
View File

@ -1155,7 +1155,7 @@ static void dwc2_work_timer(void *opaque)
static void dwc2_reset_enter(Object *obj, ResetType type)
{
DWC2Class *c = DWC2_GET_CLASS(obj);
DWC2Class *c = DWC2_USB_GET_CLASS(obj);
DWC2State *s = DWC2_USB(obj);
int i;
@ -1239,7 +1239,7 @@ static void dwc2_reset_enter(Object *obj, ResetType type)
static void dwc2_reset_hold(Object *obj)
{
DWC2Class *c = DWC2_GET_CLASS(obj);
DWC2Class *c = DWC2_USB_GET_CLASS(obj);
DWC2State *s = DWC2_USB(obj);
trace_usb_dwc2_reset_hold();
@ -1253,7 +1253,7 @@ static void dwc2_reset_hold(Object *obj)
static void dwc2_reset_exit(Object *obj)
{
DWC2Class *c = DWC2_GET_CLASS(obj);
DWC2Class *c = DWC2_USB_GET_CLASS(obj);
DWC2State *s = DWC2_USB(obj);
trace_usb_dwc2_reset_exit();
@ -1382,7 +1382,7 @@ static Property dwc2_usb_properties[] = {
static void dwc2_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
DWC2Class *c = DWC2_CLASS(klass);
DWC2Class *c = DWC2_USB_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = dwc2_realize;

4
hw/usb/hcd-dwc2.h
View File

@ -182,9 +182,9 @@ struct DWC2Class {
#define TYPE_DWC2_USB "dwc2-usb"
#define DWC2_USB(obj) \
OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
#define DWC2_CLASS(klass) \
#define DWC2_USB_CLASS(klass) \
OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
#define DWC2_GET_CLASS(obj) \
#define DWC2_USB_GET_CLASS(obj) \
OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
#endif

3
hw/vfio/pci.c
View File

@ -42,9 +42,6 @@
#include "qapi/error.h"
#include "migration/blocker.h"
#define TYPE_VFIO_PCI "vfio-pci"
#define PCI_VFIO(obj) OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI)
#define TYPE_VFIO_PCI_NOHOTPLUG "vfio-pci-nohotplug"
static void vfio_disable_interrupts(VFIOPCIDevice *vdev);

3
hw/vfio/pci.h
View File

@ -113,6 +113,9 @@ typedef struct VFIOMSIXInfo {
unsigned long *pending;
} VFIOMSIXInfo;
#define TYPE_VFIO_PCI "vfio-pci"
#define PCI_VFIO(obj) OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI)
typedef struct VFIOPCIDevice {
PCIDevice pdev;
VFIODevice vbasedev;

1
include/block/throttle-groups.h
View File

@ -59,6 +59,7 @@ typedef struct ThrottleGroupMember {
} ThrottleGroupMember;
#define TYPE_THROTTLE_GROUP "throttle-group"
typedef struct ThrottleGroup ThrottleGroup;
#define THROTTLE_GROUP(obj) OBJECT_CHECK(ThrottleGroup, (obj), TYPE_THROTTLE_GROUP)
const char *throttle_group_get_name(ThrottleGroupMember *tgm);

62
include/hw/arm/allwinner-h3.h
View File

@ -61,37 +61,37 @@
* @see AwH3State
*/
enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
AW_H3_SYSCTRL,
AW_H3_MMC0,
AW_H3_SID,
AW_H3_EHCI0,
AW_H3_OHCI0,
AW_H3_EHCI1,
AW_H3_OHCI1,
AW_H3_EHCI2,
AW_H3_OHCI2,
AW_H3_EHCI3,
AW_H3_OHCI3,
AW_H3_CCU,
AW_H3_PIT,
AW_H3_UART0,
AW_H3_UART1,
AW_H3_UART2,
AW_H3_UART3,
AW_H3_EMAC,
AW_H3_DRAMCOM,
AW_H3_DRAMCTL,
AW_H3_DRAMPHY,
AW_H3_GIC_DIST,
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
AW_H3_GIC_VCPU,
AW_H3_RTC,
AW_H3_CPUCFG,
AW_H3_SDRAM
AW_H3_DEV_SRAM_A1,
AW_H3_DEV_SRAM_A2,
AW_H3_DEV_SRAM_C,
AW_H3_DEV_SYSCTRL,
AW_H3_DEV_MMC0,
AW_H3_DEV_SID,
AW_H3_DEV_EHCI0,
AW_H3_DEV_OHCI0,
AW_H3_DEV_EHCI1,
AW_H3_DEV_OHCI1,
AW_H3_DEV_EHCI2,
AW_H3_DEV_OHCI2,
AW_H3_DEV_EHCI3,
AW_H3_DEV_OHCI3,
AW_H3_DEV_CCU,
AW_H3_DEV_PIT,
AW_H3_DEV_UART0,
AW_H3_DEV_UART1,
AW_H3_DEV_UART2,
AW_H3_DEV_UART3,
AW_H3_DEV_EMAC,
AW_H3_DEV_DRAMCOM,
AW_H3_DEV_DRAMCTL,
AW_H3_DEV_DRAMPHY,
AW_H3_DEV_GIC_DIST,
AW_H3_DEV_GIC_CPU,
AW_H3_DEV_GIC_HYP,
AW_H3_DEV_GIC_VCPU,
AW_H3_DEV_RTC,
AW_H3_DEV_CPUCFG,
AW_H3_DEV_SDRAM
};
/** Total number of CPU cores in the H3 SoC */

12
include/hw/arm/armsse.h
View File

@ -106,8 +106,8 @@
#include "hw/core/split-irq.h"
#include "hw/cpu/cluster.h"
#define TYPE_ARMSSE "arm-sse"
#define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE)
#define TYPE_ARM_SSE "arm-sse"
#define ARM_SSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARM_SSE)
/*
* These type names are for specific IoTKit subsystems; other than
@ -224,9 +224,9 @@ typedef struct ARMSSEClass {
const ARMSSEInfo *info;
} ARMSSEClass;
#define ARMSSE_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE)
#define ARMSSE_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE)
#define ARM_SSE_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARM_SSE)
#define ARM_SSE_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARM_SSE)
#endif

92
include/hw/arm/aspeed_soc.h
View File

@ -87,52 +87,52 @@ typedef struct AspeedSoCClass {
OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
enum {
ASPEED_IOMEM,
ASPEED_UART1,
ASPEED_UART2,
ASPEED_UART3,
ASPEED_UART4,
ASPEED_UART5,
ASPEED_VUART,
ASPEED_FMC,
ASPEED_SPI1,
ASPEED_SPI2,
ASPEED_EHCI1,
ASPEED_EHCI2,
ASPEED_VIC,
ASPEED_SDMC,
ASPEED_SCU,
ASPEED_ADC,
ASPEED_VIDEO,
ASPEED_SRAM,
ASPEED_SDHCI,
ASPEED_GPIO,
ASPEED_GPIO_1_8V,
ASPEED_RTC,
ASPEED_TIMER1,
ASPEED_TIMER2,
ASPEED_TIMER3,
ASPEED_TIMER4,
ASPEED_TIMER5,
ASPEED_TIMER6,
ASPEED_TIMER7,
ASPEED_TIMER8,
ASPEED_WDT,
ASPEED_PWM,
ASPEED_LPC,
ASPEED_IBT,
ASPEED_I2C,
ASPEED_ETH1,
ASPEED_ETH2,
ASPEED_ETH3,
ASPEED_ETH4,
ASPEED_MII1,
ASPEED_MII2,
ASPEED_MII3,
ASPEED_MII4,
ASPEED_SDRAM,
ASPEED_XDMA,
ASPEED_EMMC,
ASPEED_DEV_IOMEM,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
ASPEED_DEV_UART3,
ASPEED_DEV_UART4,
ASPEED_DEV_UART5,
ASPEED_DEV_VUART,
ASPEED_DEV_FMC,
ASPEED_DEV_SPI1,
ASPEED_DEV_SPI2,
ASPEED_DEV_EHCI1,
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,
ASPEED_DEV_RTC,
ASPEED_DEV_TIMER1,
ASPEED_DEV_TIMER2,
ASPEED_DEV_TIMER3,
ASPEED_DEV_TIMER4,
ASPEED_DEV_TIMER5,
ASPEED_DEV_TIMER6,
ASPEED_DEV_TIMER7,
ASPEED_DEV_TIMER8,
ASPEED_DEV_WDT,
ASPEED_DEV_PWM,
ASPEED_DEV_LPC,
ASPEED_DEV_IBT,
ASPEED_DEV_I2C,
ASPEED_DEV_ETH1,
ASPEED_DEV_ETH2,
ASPEED_DEV_ETH3,
ASPEED_DEV_ETH4,
ASPEED_DEV_MII1,
ASPEED_DEV_MII2,
ASPEED_DEV_MII3,
ASPEED_DEV_MII4,
ASPEED_DEV_SDRAM,
ASPEED_DEV_XDMA,
ASPEED_DEV_EMMC,
};
#endif /* ASPEED_SOC_H */

13
include/hw/arm/pxa.h
View File

@ -86,7 +86,10 @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
/* pxa2xx_mmci.c */
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
hwaddr base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma);
@ -94,7 +97,11 @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
qemu_irq coverswitch);
/* pxa2xx_pcmcia.c */
#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
#define PXA2XX_PCMCIA(obj) \
OBJECT_CHECK(PXA2xxPCMCIAState, obj, TYPE_PXA2XX_PCMCIA)
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
hwaddr base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
@ -119,8 +126,14 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t page_size);
I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
typedef struct PXA2xxI2SState PXA2xxI2SState;
#define PXA2XX_I2C(obj) \
OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
#define TYPE_PXA2XX_FIR "pxa2xx-fir"
typedef struct PXA2xxFIrState PXA2xxFIrState;
#define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
typedef struct {
ARMCPU *cpu;

6
include/hw/block/swim.h
View File

@ -67,10 +67,10 @@ struct SWIMCtrl {
};
#define TYPE_SWIM "swim"
#define SWIM(obj) OBJECT_CHECK(SWIM, (obj), TYPE_SWIM)
#define SWIM(obj) OBJECT_CHECK(Swim, (obj), TYPE_SWIM)
typedef struct SWIM {
typedef struct Swim {
SysBusDevice parent_obj;
SWIMCtrl ctrl;
} SWIM;
} Swim;
#endif

4
include/hw/display/macfb.h
View File

@ -40,9 +40,9 @@ typedef struct {
MacfbState macfb;
} MacfbSysBusState;
#define MACFB_NUBUS_DEVICE_CLASS(class) \
#define NUBUS_MACFB_CLASS(class) \
OBJECT_CLASS_CHECK(MacfbNubusDeviceClass, (class), TYPE_NUBUS_MACFB)
#define MACFB_NUBUS_GET_CLASS(obj) \
#define NUBUS_MACFB_GET_CLASS(obj) \
OBJECT_GET_CLASS(MacfbNubusDeviceClass, (obj), TYPE_NUBUS_MACFB)
typedef struct MacfbNubusDeviceClass {

2
include/hw/dma/i8257.h
View File

@ -5,6 +5,8 @@
#include "exec/ioport.h"
#define TYPE_I8257 "i8257"
#define I8257(obj) \
OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
typedef struct I8257Regs {
int now[2];

3
include/hw/hyperv/vmbus-bridge.h
View File

@ -11,11 +11,10 @@
#define HW_HYPERV_VMBUS_BRIDGE_H
#include "hw/sysbus.h"
#include "hw/hyperv/vmbus.h"
#define TYPE_VMBUS_BRIDGE "vmbus-bridge"
typedef struct VMBus VMBus;
typedef struct VMBusBridge {
SysBusDevice parent_obj;

4
include/hw/hyperv/vmbus.h
View File

@ -26,6 +26,10 @@
#define VMBUS_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(VMBusDeviceClass, (obj), TYPE_VMBUS_DEVICE)
#define TYPE_VMBUS "vmbus"
typedef struct VMBus VMBus;
#define VMBUS(obj) OBJECT_CHECK(VMBus, (obj), TYPE_VMBUS)
/*
* Object wrapping a GPADL -- GPA Descriptor List -- an array of guest physical
* pages, to be used for various buffers shared between the host and the guest.

5
include/hw/ide/ahci.h
View File

@ -53,11 +53,14 @@ typedef struct AHCIState {
typedef struct AHCIPCIState AHCIPCIState;
#define TYPE_ICH9_AHCI "ich9-ahci"
#define ICH_AHCI(obj) \
OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
int32_t ahci_get_num_ports(PCIDevice *dev);
void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
#define TYPE_SYSBUS_AHCI "sysbus-ahci"
#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
typedef struct SysbusAHCIState {
/*< private >*/
@ -69,6 +72,8 @@ typedef struct SysbusAHCIState {
} SysbusAHCIState;
#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
#define ALLWINNER_AHCI(obj) \
OBJECT_CHECK(AllwinnerAHCIState, (obj), TYPE_ALLWINNER_AHCI)
#define ALLWINNER_AHCI_MMIO_OFF 0x80
#define ALLWINNER_AHCI_MMIO_SIZE 0x80

1
include/hw/input/i8042.h
View File

@ -11,6 +11,7 @@
#include "hw/isa/isa.h"
#define TYPE_I8042 "i8042"
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
#define I8042_A20_LINE "a20"

1
include/hw/m68k/mcf_fec.h
View File

@ -11,6 +11,7 @@
#define HW_M68K_MCF_FEC_H
#define TYPE_MCF_FEC_NET "mcf-fec"
typedef struct mcf_fec_state mcf_fec_state;
#define MCF_FEC_NET(obj) OBJECT_CHECK(mcf_fec_state, (obj), TYPE_MCF_FEC_NET)
#define FEC_NUM_IRQ 13

3
include/hw/misc/auxbus.h
View File

@ -32,7 +32,10 @@ typedef struct AUXBus AUXBus;
typedef struct AUXSlave AUXSlave;
typedef enum AUXCommand AUXCommand;
typedef enum AUXReply AUXReply;
#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
typedef struct AUXTOI2CState AUXTOI2CState;
#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
enum AUXCommand {
WRITE_I2C = 0,

1
include/hw/nubus/nubus.h
View File

@ -29,7 +29,6 @@
#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS)
#define TYPE_NUBUS_BRIDGE "nubus-bridge"
#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRIDGE)
typedef struct NubusBus {
BusState qbus;

1
include/hw/pci/pci.h
View File

@ -396,6 +396,7 @@ typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
#define TYPE_PCI_BUS "PCI"
typedef struct PCIBusClass PCIBusClass;
#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
#define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
#define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)

4
include/hw/pci/pci_bus.h
View File

@ -10,14 +10,14 @@
* use accessor functions in pci.h
*/
typedef struct PCIBusClass {
struct PCIBusClass {
/*< private >*/
BusClass parent_class;
/*< public >*/
int (*bus_num)(PCIBus *bus);
uint16_t (*numa_node)(PCIBus *bus);
} PCIBusClass;
};
enum PCIBusFlags {
/* This bus is the root of a PCI domain */

4
include/hw/platform-bus.h
View File

@ -29,10 +29,6 @@ typedef struct PlatformBusDevice PlatformBusDevice;
#define TYPE_PLATFORM_BUS_DEVICE "platform-bus-device"
#define PLATFORM_BUS_DEVICE(obj) \
OBJECT_CHECK(PlatformBusDevice, (obj), TYPE_PLATFORM_BUS_DEVICE)
#define PLATFORM_BUS_DEVICE_CLASS(klass) \
OBJECT_CLASS_CHECK(PlatformBusDeviceClass, (klass), TYPE_PLATFORM_BUS_DEVICE)
#define PLATFORM_BUS_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(PlatformBusDeviceClass, (obj), TYPE_PLATFORM_BUS_DEVICE)
struct PlatformBusDevice {
/*< private >*/

1
include/hw/ppc/spapr.h
View File

@ -41,6 +41,7 @@ typedef struct SpaprDimmState SpaprDimmState;
typedef struct SpaprMachineClass SpaprMachineClass;
#define TYPE_SPAPR_MACHINE "spapr-machine"
typedef struct SpaprMachineState SpaprMachineState;
#define SPAPR_MACHINE(obj) \
OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE)
#define SPAPR_MACHINE_GET_CLASS(obj) \

36
include/hw/ppc/spapr_irq.h
View File

@ -28,7 +28,7 @@
#define SPAPR_NR_XIRQS 0x1000
typedef struct SpaprMachineState SpaprMachineState;
struct SpaprMachineState;
typedef struct SpaprInterruptController SpaprInterruptController;
@ -67,20 +67,20 @@ typedef struct SpaprInterruptControllerClass {
int (*post_load)(SpaprInterruptController *intc, int version_id);
} SpaprInterruptControllerClass;
void spapr_irq_update_active_intc(SpaprMachineState *spapr);
void spapr_irq_update_active_intc(struct SpaprMachineState *spapr);
int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
int spapr_irq_cpu_intc_create(struct SpaprMachineState *spapr,
PowerPCCPU *cpu, Error **errp);
void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon);
void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
void spapr_irq_cpu_intc_reset(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_cpu_intc_destroy(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_print_info(struct SpaprMachineState *spapr, Monitor *mon);
void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers,
void *fdt, uint32_t phandle);
uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr);
int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
uint32_t spapr_irq_nr_msis(struct SpaprMachineState *spapr);
int spapr_irq_msi_alloc(struct SpaprMachineState *spapr, uint32_t num, bool align,
Error **errp);
void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
void spapr_irq_msi_free(struct SpaprMachineState *spapr, int irq, uint32_t num);
typedef struct SpaprIrq {
bool xics;
@ -92,13 +92,13 @@ extern SpaprIrq spapr_irq_xics_legacy;
extern SpaprIrq spapr_irq_xive;
extern SpaprIrq spapr_irq_dual;
void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
void spapr_irq_init(struct SpaprMachineState *spapr, Error **errp);
int spapr_irq_claim(struct SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
void spapr_irq_free(struct SpaprMachineState *spapr, int irq, int num);
qemu_irq spapr_qirq(struct SpaprMachineState *spapr, int irq);
int spapr_irq_post_load(struct SpaprMachineState *spapr, int version_id);
void spapr_irq_reset(struct SpaprMachineState *spapr, Error **errp);
int spapr_irq_get_phandle(struct SpaprMachineState *spapr, void *fdt, Error **errp);
typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *,
uint32_t, Error **);
@ -111,7 +111,7 @@ int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
/*
* XICS legacy routines
*/
int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
int spapr_irq_find(struct SpaprMachineState *spapr, int num, bool align, Error **errp);
#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
#endif

3
include/hw/ppc/spapr_xive.h
View File

@ -66,7 +66,8 @@ typedef struct SpaprXiveClass {
void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
void spapr_xive_hcall_init(SpaprMachineState *spapr);
struct SpaprMachineState;
void spapr_xive_hcall_init(struct SpaprMachineState *spapr);
void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
void spapr_xive_map_mmio(SpaprXive *xive);

38
include/hw/riscv/opentitan.h
View File

@ -49,25 +49,25 @@ typedef struct OpenTitanState {
} OpenTitanState;
enum {
IBEX_ROM,
IBEX_RAM,
IBEX_FLASH,
IBEX_UART,
IBEX_GPIO,
IBEX_SPI,
IBEX_FLASH_CTRL,
IBEX_RV_TIMER,
IBEX_AES,
IBEX_HMAC,
IBEX_PLIC,
IBEX_PWRMGR,
IBEX_RSTMGR,
IBEX_CLKMGR,
IBEX_PINMUX,
IBEX_ALERT_HANDLER,
IBEX_NMI_GEN,
IBEX_USBDEV,
IBEX_PADCTRL,
IBEX_DEV_ROM,
IBEX_DEV_RAM,
IBEX_DEV_FLASH,
IBEX_DEV_UART,
IBEX_DEV_GPIO,
IBEX_DEV_SPI,
IBEX_DEV_FLASH_CTRL,
IBEX_DEV_RV_TIMER,
IBEX_DEV_AES,
IBEX_DEV_HMAC,
IBEX_DEV_PLIC,
IBEX_DEV_PWRMGR,
IBEX_DEV_RSTMGR,
IBEX_DEV_CLKMGR,
IBEX_DEV_PINMUX,
IBEX_DEV_ALERT_HANDLER,
IBEX_DEV_NMI_GEN,
IBEX_DEV_USBDEV,
IBEX_DEV_PADCTRL,
};
enum {

1
include/hw/s390x/event-facility.h
View File

@ -195,6 +195,7 @@ typedef struct SCLPEventClass {
} SCLPEventClass;
#define TYPE_SCLP_EVENT_FACILITY "s390-sclp-event-facility"
typedef struct SCLPEventFacility SCLPEventFacility;
#define EVENT_FACILITY(obj) \
OBJECT_CHECK(SCLPEventFacility, (obj), TYPE_SCLP_EVENT_FACILITY)
#define EVENT_FACILITY_CLASS(klass) \

2
include/hw/s390x/s390-virtio-ccw.h
View File

@ -18,7 +18,7 @@
#define S390_CCW_MACHINE(obj) \
OBJECT_CHECK(S390CcwMachineState, (obj), TYPE_S390_CCW_MACHINE)
#define S390_MACHINE_CLASS(klass) \
#define S390_CCW_MACHINE_CLASS(klass) \
OBJECT_CLASS_CHECK(S390CcwMachineClass, (klass), TYPE_S390_CCW_MACHINE)
typedef struct S390CcwMachineState {

1
include/hw/s390x/s390_flic.h
View File

@ -75,6 +75,7 @@ typedef struct S390FLICStateClass {
} S390FLICStateClass;
#define TYPE_KVM_S390_FLIC "s390-flic-kvm"
typedef struct KVMS390FLICState KVMS390FLICState;
#define KVM_S390_FLIC(obj) \
OBJECT_CHECK(KVMS390FLICState, (obj), TYPE_KVM_S390_FLIC)

4
include/hw/s390x/sclp.h
View File

@ -185,12 +185,12 @@ typedef struct SCCB {
#define SCLP_CLASS(oc) OBJECT_CLASS_CHECK(SCLPDeviceClass, (oc), TYPE_SCLP)
#define SCLP_GET_CLASS(obj) OBJECT_GET_CLASS(SCLPDeviceClass, (obj), TYPE_SCLP)
typedef struct SCLPEventFacility SCLPEventFacility;
struct SCLPEventFacility;
typedef struct SCLPDevice {
/* private */
DeviceState parent_obj;
SCLPEventFacility *event_facility;
struct SCLPEventFacility *event_facility;
int increment_size;
/* public */

4
include/hw/southbridge/piix.h
View File

@ -64,6 +64,10 @@ typedef struct PIIXState {
MemoryRegion rcr_mem;
} PIIX3State;
#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
#define PIIX3_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
extern PCIDevice *piix4_dev;
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);

2
include/hw/timer/aspeed_timer.h
View File

@ -26,7 +26,7 @@
#include "hw/misc/aspeed_scu.h"
#define ASPEED_TIMER(obj) \
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER)
#define TYPE_ASPEED_TIMER "aspeed.timer"
#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"

2
include/hw/timer/i8254.h
View File

@ -39,6 +39,8 @@ typedef struct PITChannelInfo {
} PITChannelInfo;
#define TYPE_PIT_COMMON "pit-common"
typedef struct PITCommonState PITCommonState;
typedef struct PITCommonClass PITCommonClass;
#define PIT_COMMON(obj) \
OBJECT_CHECK(PITCommonState, (obj), TYPE_PIT_COMMON)
#define PIT_COMMON_CLASS(klass) \

8
include/hw/timer/i8254_internal.h
View File

@ -50,14 +50,14 @@ typedef struct PITChannelState {
uint32_t irq_disabled;
} PITChannelState;
typedef struct PITCommonState {
struct PITCommonState {
ISADevice dev;
MemoryRegion ioports;
uint32_t iobase;
PITChannelState channels[3];
} PITCommonState;
};
typedef struct PITCommonClass {
struct PITCommonClass {
ISADeviceClass parent_class;
void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
@ -65,7 +65,7 @@ typedef struct PITCommonClass {
PITChannelInfo *info);
void (*pre_save)(PITCommonState *s);
void (*post_load)(PITCommonState *s);
} PITCommonClass;
};
int pit_get_out(PITChannelState *s, int64_t current_time);
int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time);

2
include/hw/virtio/virtio-gpu.h
View File

@ -36,6 +36,8 @@
OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU)
#define TYPE_VHOST_USER_GPU "vhost-user-gpu"
#define VHOST_USER_GPU(obj) \
OBJECT_CHECK(VhostUserGPU, (obj), TYPE_VHOST_USER_GPU)
#define VIRTIO_ID_GPU 16

5
include/hw/virtio/virtio-serial.h
View File

@ -33,7 +33,12 @@ struct virtio_serial_conf {
OBJECT_GET_CLASS(VirtIOSerialPortClass, (obj), TYPE_VIRTIO_SERIAL_PORT)
typedef struct VirtIOSerial VirtIOSerial;
#define TYPE_VIRTIO_SERIAL_BUS "virtio-serial-bus"
typedef struct VirtIOSerialBus VirtIOSerialBus;
#define VIRTIO_SERIAL_BUS(obj) \
OBJECT_CHECK(VirtIOSerialBus, (obj), TYPE_VIRTIO_SERIAL_BUS)
typedef struct VirtIOSerialPort VirtIOSerialPort;
typedef struct VirtIOSerialPortClass {

1
include/hw/xen/xen-legacy-backend.h
View File

@ -9,6 +9,7 @@
#define TYPE_XENSYSBUS "xen-sysbus"
#define TYPE_XENBACKEND "xen-backend"
typedef struct XenLegacyDevice XenLegacyDevice;
#define XENBACKEND_DEVICE(obj) \
OBJECT_CHECK(XenLegacyDevice, (obj), TYPE_XENBACKEND)

4
include/net/can_emu.h
View File

@ -100,10 +100,6 @@ struct CanBusClientState {
};
#define TYPE_CAN_BUS "can-bus"
#define CAN_BUS_CLASS(klass) \
OBJECT_CLASS_CHECK(CanBusClass, (klass), TYPE_CAN_BUS)
#define CAN_BUS_GET_CLASS(obj) \
OBJECT_GET_CLASS(CanBusClass, (obj), TYPE_CAN_BUS)
#define CAN_BUS(obj) \
OBJECT_CHECK(CanBusState, (obj), TYPE_CAN_BUS)

3
include/sysemu/hvf.h
View File

@ -13,6 +13,8 @@
#ifndef HVF_H
#define HVF_H
#include "sysemu/accel.h"
#ifdef CONFIG_HVF
uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
int reg);
@ -33,6 +35,7 @@ void hvf_vcpu_destroy(CPUState *);
#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
typedef struct HVFState HVFState;
#define HVF_STATE(obj) \
OBJECT_CHECK(HVFState, (obj), TYPE_HVF_ACCEL)

6
include/sysemu/kvm.h
View File

@ -17,6 +17,7 @@
#include "qemu/queue.h"
#include "hw/core/cpu.h"
#include "exec/memattrs.h"
#include "sysemu/accel.h"
#ifdef NEED_CPU_H
# ifdef CONFIG_KVM
@ -199,7 +200,12 @@ typedef struct KVMCapabilityInfo {
#define KVM_CAP_LAST_INFO { NULL, 0 }
struct KVMState;
#define TYPE_KVM_ACCEL ACCEL_CLASS_NAME("kvm")
typedef struct KVMState KVMState;
#define KVM_STATE(obj) \
OBJECT_CHECK(KVMState, (obj), TYPE_KVM_ACCEL)
extern KVMState *kvm_state;
typedef struct Notifier Notifier;

5
include/sysemu/kvm_int.h
View File

@ -33,11 +33,6 @@ typedef struct KVMMemoryListener {
int as_id;
} KVMMemoryListener;
#define TYPE_KVM_ACCEL ACCEL_CLASS_NAME("kvm")
#define KVM_STATE(obj) \
OBJECT_CHECK(KVMState, (obj), TYPE_KVM_ACCEL)
void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml,
AddressSpace *as, int as_id);

4
migration/migration.h
View File

@ -114,11 +114,11 @@ void fill_destination_postcopy_migration_info(MigrationInfo *info);
#define TYPE_MIGRATION "migration"
#define MIGRATION_CLASS(klass) \
#define MIGRATION_OBJ_CLASS(klass) \
OBJECT_CLASS_CHECK(MigrationClass, (klass), TYPE_MIGRATION)
#define MIGRATION_OBJ(obj) \
OBJECT_CHECK(MigrationState, (obj), TYPE_MIGRATION)
#define MIGRATION_GET_CLASS(obj) \
#define MIGRATION_OBJ_GET_CLASS(obj) \
OBJECT_GET_CLASS(MigrationClass, (obj), TYPE_MIGRATION)
typedef struct MigrationClass {

4
target/i386/hvf/hvf-i386.h
View File

@ -57,13 +57,13 @@ typedef struct hvf_vcpu_caps {
uint64_t vmx_cap_preemption_timer;
} hvf_vcpu_caps;
typedef struct HVFState {
struct HVFState {
AccelState parent;
hvf_slot slots[32];
int num_slots;
hvf_vcpu_caps *hvf_caps;
} HVFState;
};
extern HVFState *hvf_state;
void hvf_set_phys_mem(MemoryRegionSection *, bool);