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https://github.com/xemu-project/xemu.git
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SPARC: Emulation of GRLIB IRQMP
This device exposes two parameters: - set_pil_in (ptr) : A function to set the pil_in of the SPARC CPU - set_pil_in_opaque (ptr) : Opaque argument of the set_pil_in function Emulation of GrLib devices is base on the GRLIB IP Core User's Manual: http://www.gaisler.com/products/grlib/grip.pdf Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Fabien Chouteau
Blue Swirl
parent
0f3a4a01eb
commit
3f10bcbb64
38
hw/grlib.h
38
hw/grlib.h
@ -32,6 +32,44 @@
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* http://www.gaisler.com/products/grlib/grip.pdf
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*/
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/* IRQMP */
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typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
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void grlib_irqmp_set_irq(void *opaque, int irq, int level);
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void grlib_irqmp_ack(DeviceState *dev, int intno);
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static inline
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DeviceState *grlib_irqmp_create(target_phys_addr_t base,
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CPUState *env,
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qemu_irq **cpu_irqs,
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uint32_t nr_irqs,
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set_pil_in_fn set_pil_in)
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{
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DeviceState *dev;
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assert(cpu_irqs != NULL);
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dev = qdev_create(NULL, "grlib,irqmp");
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qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
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qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
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if (qdev_init(dev)) {
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return NULL;
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}
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env->irq_manager = dev;
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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*cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
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dev,
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nr_irqs);
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return dev;
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}
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/* GPTimer */
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static inline
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376
hw/grlib_irqmp.c
Normal file
376
hw/grlib_irqmp.c
Normal file
@ -0,0 +1,376 @@
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/*
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* QEMU GRLIB IRQMP Emulator
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*
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* (Multiprocessor and extended interrupt not supported)
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*
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* Copyright (c) 2010-2011 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "cpu.h"
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#include "grlib.h"
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#include "trace.h"
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#define IRQMP_MAX_CPU 16
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#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
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/* Memory mapped register offsets */
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#define LEVEL_OFFSET 0x00
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#define PENDING_OFFSET 0x04
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#define FORCE0_OFFSET 0x08
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#define CLEAR_OFFSET 0x0C
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#define MP_STATUS_OFFSET 0x10
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#define BROADCAST_OFFSET 0x14
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#define MASK_OFFSET 0x40
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#define FORCE_OFFSET 0x80
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#define EXTENDED_OFFSET 0xC0
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typedef struct IRQMPState IRQMPState;
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typedef struct IRQMP {
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SysBusDevice busdev;
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void *set_pil_in;
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void *set_pil_in_opaque;
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IRQMPState *state;
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} IRQMP;
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struct IRQMPState {
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uint32_t level;
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uint32_t pending;
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uint32_t clear;
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uint32_t broadcast;
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uint32_t mask[IRQMP_MAX_CPU];
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uint32_t force[IRQMP_MAX_CPU];
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uint32_t extended[IRQMP_MAX_CPU];
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IRQMP *parent;
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};
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static void grlib_irqmp_check_irqs(IRQMPState *state)
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{
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uint32_t pend = 0;
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uint32_t level0 = 0;
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uint32_t level1 = 0;
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set_pil_in_fn set_pil_in;
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assert(state != NULL);
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assert(state->parent != NULL);
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/* IRQ for CPU 0 (no SMP support) */
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pend = (state->pending | state->force[0])
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& state->mask[0];
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level0 = pend & ~state->level;
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level1 = pend & state->level;
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trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
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state->mask[0], level1, level0);
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set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
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/* Trigger level1 interrupt first and level0 if there is no level1 */
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if (level1 != 0) {
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set_pil_in(state->parent->set_pil_in_opaque, level1);
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} else {
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set_pil_in(state->parent->set_pil_in_opaque, level0);
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}
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}
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void grlib_irqmp_ack(DeviceState *dev, int intno)
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{
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SysBusDevice *sdev;
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IRQMP *irqmp;
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IRQMPState *state;
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uint32_t mask;
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assert(dev != NULL);
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sdev = sysbus_from_qdev(dev);
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assert(sdev != NULL);
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irqmp = FROM_SYSBUS(typeof(*irqmp), sdev);
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assert(irqmp != NULL);
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state = irqmp->state;
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assert(state != NULL);
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intno &= 15;
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mask = 1 << intno;
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trace_grlib_irqmp_ack(intno);
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/* Clear registers */
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state->pending &= ~mask;
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state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
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grlib_irqmp_check_irqs(state);
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}
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void grlib_irqmp_set_irq(void *opaque, int irq, int level)
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{
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IRQMP *irqmp;
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IRQMPState *s;
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int i = 0;
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assert(opaque != NULL);
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irqmp = FROM_SYSBUS(typeof(*irqmp), sysbus_from_qdev(opaque));
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assert(irqmp != NULL);
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s = irqmp->state;
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assert(s != NULL);
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assert(s->parent != NULL);
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if (level) {
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trace_grlib_irqmp_set_irq(irq);
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if (s->broadcast & 1 << irq) {
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/* Broadcasted IRQ */
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for (i = 0; i < IRQMP_MAX_CPU; i++) {
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s->force[i] |= 1 << irq;
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}
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} else {
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s->pending |= 1 << irq;
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}
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grlib_irqmp_check_irqs(s);
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}
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}
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static uint32_t grlib_irqmp_readl(void *opaque, target_phys_addr_t addr)
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{
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IRQMP *irqmp = opaque;
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IRQMPState *state;
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assert(irqmp != NULL);
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state = irqmp->state;
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assert(state != NULL);
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addr &= 0xff;
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/* global registers */
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switch (addr) {
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case LEVEL_OFFSET:
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return state->level;
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case PENDING_OFFSET:
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return state->pending;
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case FORCE0_OFFSET:
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/* This register is an "alias" for the force register of CPU 0 */
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return state->force[0];
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case CLEAR_OFFSET:
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case MP_STATUS_OFFSET:
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/* Always read as 0 */
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return 0;
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case BROADCAST_OFFSET:
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return state->broadcast;
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default:
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break;
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}
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/* mask registers */
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if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
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int cpu = (addr - MASK_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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return state->mask[cpu];
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}
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/* force registers */
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if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
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int cpu = (addr - FORCE_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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return state->force[cpu];
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}
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/* extended (not supported) */
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if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
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int cpu = (addr - EXTENDED_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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return state->extended[cpu];
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}
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trace_grlib_irqmp_unknown_register("read", addr);
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return 0;
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}
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static void
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grlib_irqmp_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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IRQMP *irqmp = opaque;
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IRQMPState *state;
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assert(irqmp != NULL);
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state = irqmp->state;
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assert(state != NULL);
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addr &= 0xff;
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/* global registers */
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switch (addr) {
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case LEVEL_OFFSET:
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value &= 0xFFFF << 1; /* clean up the value */
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state->level = value;
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return;
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case PENDING_OFFSET:
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/* Read Only */
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return;
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case FORCE0_OFFSET:
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/* This register is an "alias" for the force register of CPU 0 */
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value &= 0xFFFE; /* clean up the value */
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state->force[0] = value;
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grlib_irqmp_check_irqs(irqmp->state);
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return;
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case CLEAR_OFFSET:
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value &= ~1; /* clean up the value */
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state->pending &= ~value;
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return;
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case MP_STATUS_OFFSET:
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/* Read Only (no SMP support) */
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return;
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case BROADCAST_OFFSET:
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value &= 0xFFFE; /* clean up the value */
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state->broadcast = value;
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return;
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default:
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break;
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}
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/* mask registers */
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if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
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int cpu = (addr - MASK_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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value &= ~1; /* clean up the value */
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state->mask[cpu] = value;
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grlib_irqmp_check_irqs(irqmp->state);
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return;
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}
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/* force registers */
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if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
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int cpu = (addr - FORCE_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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uint32_t force = value & 0xFFFE;
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uint32_t clear = (value >> 16) & 0xFFFE;
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uint32_t old = state->force[cpu];
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state->force[cpu] = (old | force) & ~clear;
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grlib_irqmp_check_irqs(irqmp->state);
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return;
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}
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/* extended (not supported) */
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if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
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int cpu = (addr - EXTENDED_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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value &= 0xF; /* clean up the value */
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state->extended[cpu] = value;
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return;
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}
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trace_grlib_irqmp_unknown_register("write", addr);
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}
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static CPUReadMemoryFunc * const grlib_irqmp_read[] = {
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NULL, NULL, &grlib_irqmp_readl,
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};
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static CPUWriteMemoryFunc * const grlib_irqmp_write[] = {
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NULL, NULL, &grlib_irqmp_writel,
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};
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static void grlib_irqmp_reset(DeviceState *d)
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{
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IRQMP *irqmp = container_of(d, IRQMP, busdev.qdev);
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assert(irqmp != NULL);
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assert(irqmp->state != NULL);
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memset(irqmp->state, 0, sizeof *irqmp->state);
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irqmp->state->parent = irqmp;
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}
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static int grlib_irqmp_init(SysBusDevice *dev)
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{
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IRQMP *irqmp = FROM_SYSBUS(typeof(*irqmp), dev);
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int irqmp_regs;
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assert(irqmp != NULL);
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/* Check parameters */
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if (irqmp->set_pil_in == NULL) {
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return -1;
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}
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irqmp_regs = cpu_register_io_memory(grlib_irqmp_read,
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grlib_irqmp_write,
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irqmp, DEVICE_NATIVE_ENDIAN);
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irqmp->state = qemu_mallocz(sizeof *irqmp->state);
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if (irqmp_regs < 0) {
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return -1;
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}
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sysbus_init_mmio(dev, IRQMP_REG_SIZE, irqmp_regs);
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return 0;
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}
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static SysBusDeviceInfo grlib_irqmp_info = {
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.init = grlib_irqmp_init,
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.qdev.name = "grlib,irqmp",
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.qdev.reset = grlib_irqmp_reset,
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.qdev.size = sizeof(IRQMP),
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.qdev.props = (Property[]) {
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DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
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DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void grlib_irqmp_register(void)
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{
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sysbus_register_withprop(&grlib_irqmp_info);
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}
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device_init(grlib_irqmp_register)
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@ -234,3 +234,9 @@ disable grlib_gptimer_hit(int id) "timer:%d HIT"
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disable grlib_gptimer_readl(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
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disable grlib_gptimer_writel(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
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disable grlib_gptimer_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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# hw/grlib_irqmp.c
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disable grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n"
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disable grlib_irqmp_ack(int intno) "interrupt:%d"
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disable grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
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disable grlib_irqmp_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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