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https://github.com/xemu-project/xemu.git
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target-arm queue:
* Fix reset GPIO handling for spitz, tosa boards
* virt: add 'pmu' property for configuring whether to expose the
vPMU to the guest
* char: cadence: correct reset value for baud rate registers
* versatilepb: do not run if user asks for more than 256MB RAM
* pxa2xx: Set value default values for CCCR and CKEN on PXA255
* arm: cubieboard: Add support for initrd
* i.MX: Fix GPIO ISR register write
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161028' into staging
target-arm queue:
* Fix reset GPIO handling for spitz, tosa boards
* virt: add 'pmu' property for configuring whether to expose the
vPMU to the guest
* char: cadence: correct reset value for baud rate registers
* versatilepb: do not run if user asks for more than 256MB RAM
* pxa2xx: Set value default values for CCCR and CKEN on PXA255
* arm: cubieboard: Add support for initrd
* i.MX: Fix GPIO ISR register write
# gpg: Signature made Fri 28 Oct 2016 15:56:56 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20161028:
hw/arm/tosa: Fix reset handling
hw/arm/spitz: Fix reset handling
arm: virt: add PMU property to mach-virt machine type
arm: Add an option to turn on/off vPMU support
char: cadence: correct reset value for baud rate registers
versatilepb: do not run if user asks for more than 256MB RAM
hw/arm/pxa2xx: Set value default values for CCCR and CKEN on PXA255
arm: cubieboard: Add support for initrd
i.MX: Fix GPIO ISR register write
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
4178c782f8
@ -74,6 +74,7 @@ static void cubieboard_init(MachineState *machine)
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cubieboard_binfo.ram_size = machine->ram_size;
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cubieboard_binfo.kernel_filename = machine->kernel_filename;
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cubieboard_binfo.kernel_cmdline = machine->kernel_cmdline;
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cubieboard_binfo.initrd_filename = machine->initrd_filename;
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arm_load_kernel(&s->a10->cpu, &cubieboard_binfo);
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}
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@ -2267,7 +2267,9 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
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s->cm_base = 0x41300000;
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s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
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s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */
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s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */
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s->clkcfg = 0x00000009; /* Turbo mode active */
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memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
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memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
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@ -29,6 +29,7 @@
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#include "sysemu/block-backend.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#undef REG_FMT
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#define REG_FMT "0x%02lx"
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@ -844,9 +845,18 @@ static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
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spitz_hsync ^= 1;
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}
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static void spitz_reset(void *opaque, int line, int level)
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{
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if (level) {
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qemu_system_reset_request();
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}
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}
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static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
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{
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qemu_irq lcd_hsync;
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qemu_irq reset;
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/*
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* Bad hack: We toggle the LCD hsync GPIO on every GPIO status
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* read to satisfy broken guests that poll-wait for hsync.
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@ -867,7 +877,8 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
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qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
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/* Handle reset */
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qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
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reset = qemu_allocate_irq(spitz_reset, cpu, 0);
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qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, reset);
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/* PCMCIA signals: card's IRQ and Card-Detect */
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if (slots >= 1)
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@ -25,6 +25,7 @@
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#include "sysemu/block-backend.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#define TOSA_RAM 0x04000000
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#define TOSA_ROM 0x00800000
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@ -86,6 +87,12 @@ static void tosa_out_switch(void *opaque, int line, int level)
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}
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}
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static void tosa_reset(void *opaque, int line, int level)
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{
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if (level) {
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qemu_system_reset_request();
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}
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}
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static void tosa_gpio_setup(PXA2xxState *cpu,
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DeviceState *scp0,
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@ -93,13 +100,16 @@ static void tosa_gpio_setup(PXA2xxState *cpu,
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TC6393xbState *tmio)
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{
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qemu_irq *outsignals = qemu_allocate_irqs(tosa_out_switch, cpu, 4);
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qemu_irq reset;
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/* MMC/SD host */
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pxa2xx_mmci_handlers(cpu->mmc,
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qdev_get_gpio_in(scp0, TOSA_GPIO_SD_WP),
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qemu_irq_invert(qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_nSD_DETECT)));
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/* Handle reset */
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qdev_connect_gpio_out(cpu->gpio, TOSA_GPIO_ON_RESET, cpu->reset);
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reset = qemu_allocate_irq(tosa_reset, cpu, 0);
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qdev_connect_gpio_out(cpu->gpio, TOSA_GPIO_ON_RESET, reset);
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/* PCMCIA signals: card's IRQ and Card-Detect */
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pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
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@ -198,6 +198,15 @@ static void versatile_init(MachineState *machine, int board_id)
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int done_smc = 0;
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DriveInfo *dinfo;
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if (machine->ram_size > 0x10000000) {
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/* Device starting at address 0x10000000,
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* and memory cannot overlap with devices.
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* Refuse to run rather than behaving very confusingly.
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*/
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error_report("versatilepb: memory size must not exceed 256MB");
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exit(1);
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}
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if (!machine->cpu_model) {
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machine->cpu_model = "arm926";
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}
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@ -594,7 +594,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
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gicc->uid = i;
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gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
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if (armcpu->has_pmu) {
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if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
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gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
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}
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}
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@ -85,6 +85,7 @@ typedef struct {
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VirtBoardInfo *daughterboard;
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bool disallow_affinity_adjustment;
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bool no_its;
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bool no_pmu;
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} VirtMachineClass;
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typedef struct {
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@ -490,7 +491,7 @@ static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype)
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CPU_FOREACH(cpu) {
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armcpu = ARM_CPU(cpu);
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if (!armcpu->has_pmu ||
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if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) ||
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!kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) {
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return;
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}
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@ -1353,6 +1354,10 @@ static void machvirt_init(MachineState *machine)
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}
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}
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if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
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object_property_set_bool(cpuobj, false, "pmu", NULL);
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}
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if (object_property_find(cpuobj, "reset-cbar", NULL)) {
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object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base,
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"reset-cbar", &error_abort);
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@ -1592,5 +1597,7 @@ static void virt_machine_2_6_options(MachineClass *mc)
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virt_machine_2_7_options(mc);
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SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
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vmc->disallow_affinity_adjustment = true;
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/* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
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vmc->no_pmu = true;
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}
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DEFINE_VIRT_MACHINE(2, 6)
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@ -450,7 +450,8 @@ static void cadence_uart_reset(DeviceState *dev)
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s->r[R_IMR] = 0;
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s->r[R_CISR] = 0;
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s->r[R_RTRIG] = 0x00000020;
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s->r[R_BRGR] = 0x0000000F;
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s->r[R_BRGR] = 0x0000028B;
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s->r[R_BDIV] = 0x0000000F;
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s->r[R_TTRIG] = 0x00000020;
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uart_rx_reset(s);
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@ -237,7 +237,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
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break;
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case ISR_ADDR:
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s->isr |= ~value;
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s->isr &= ~value;
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imx_gpio_set_all_int_lines(s);
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break;
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@ -19,6 +19,7 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "internals.h"
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@ -496,6 +497,10 @@ static Property arm_cpu_rvbar_property =
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static Property arm_cpu_has_el3_property =
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DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
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/* use property name "pmu" to match other archs and virt tools */
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static Property arm_cpu_has_pmu_property =
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DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
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static Property arm_cpu_has_mpu_property =
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DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
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@ -539,6 +544,11 @@ static void arm_cpu_post_init(Object *obj)
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#endif
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
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&error_abort);
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
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&error_abort);
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@ -677,6 +687,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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cpu->id_aa64pfr0 &= ~0xf000;
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}
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if (!cpu->has_pmu || !kvm_enabled()) {
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cpu->has_pmu = false;
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unset_feature(env, ARM_FEATURE_PMU);
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}
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if (!arm_feature(env, ARM_FEATURE_EL2)) {
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/* Disable the hypervisor feature bits in the processor feature
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* registers if we don't have EL2. These are id_pfr1[15:12] and
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@ -1124,6 +1124,7 @@ enum arm_features {
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ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
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ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
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ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
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ARM_FEATURE_PMU, /* has PMU support */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -111,6 +111,7 @@ static void aarch64_a57_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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@ -166,6 +167,7 @@ static void aarch64_a53_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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cpu->midr = 0x410fd034;
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cpu->revidr = 0x00000000;
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@ -428,6 +428,11 @@ static inline void set_feature(uint64_t *features, int feature)
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*features |= 1ULL << feature;
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}
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static inline void unset_feature(uint64_t *features, int feature)
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{
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*features &= ~(1ULL << feature);
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}
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bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
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{
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/* Identify the feature bits corresponding to the host CPU, and
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@ -469,6 +474,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
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set_feature(&features, ARM_FEATURE_VFP4);
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set_feature(&features, ARM_FEATURE_NEON);
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set_feature(&features, ARM_FEATURE_AARCH64);
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set_feature(&features, ARM_FEATURE_PMU);
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ahcc->features = features;
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@ -482,6 +488,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
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int ret;
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uint64_t mpidr;
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
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!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
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@ -501,10 +508,14 @@ int kvm_arch_init_vcpu(CPUState *cs)
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if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
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cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
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}
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if (kvm_irqchip_in_kernel() &&
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kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
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cpu->has_pmu = true;
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if (!kvm_irqchip_in_kernel() ||
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!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
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cpu->has_pmu = false;
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}
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if (cpu->has_pmu) {
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cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
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} else {
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unset_feature(&env->features, ARM_FEATURE_PMU);
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}
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/* Do KVM_ARM_VCPU_INIT ioctl */
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