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https://github.com/xemu-project/xemu.git
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bfd.h dependancy removed
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@75 c046a42c-6fe2-441c-8c8c-71466251a162
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149
dis-asm.h
149
dis-asm.h
@ -11,7 +11,152 @@
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#include <stdio.h>
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#include <string.h>
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#include "bfd.h"
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#include <inttypes.h>
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#define PARAMS(x) x
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typedef void *PTR;
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typedef uint64_t bfd_vma;
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typedef uint8_t bfd_byte;
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enum bfd_flavour {
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bfd_target_unknown_flavour,
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bfd_target_aout_flavour,
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bfd_target_coff_flavour,
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bfd_target_ecoff_flavour,
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bfd_target_elf_flavour,
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bfd_target_ieee_flavour,
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bfd_target_nlm_flavour,
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bfd_target_oasys_flavour,
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bfd_target_tekhex_flavour,
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bfd_target_srec_flavour,
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bfd_target_ihex_flavour,
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bfd_target_som_flavour,
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bfd_target_os9k_flavour,
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bfd_target_versados_flavour,
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bfd_target_msdos_flavour,
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bfd_target_evax_flavour
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};
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enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
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enum bfd_architecture
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{
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bfd_arch_unknown, /* File arch not known */
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bfd_arch_obscure, /* Arch known, not one of these */
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bfd_arch_m68k, /* Motorola 68xxx */
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#define bfd_mach_m68000 1
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#define bfd_mach_m68008 2
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#define bfd_mach_m68010 3
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#define bfd_mach_m68020 4
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#define bfd_mach_m68030 5
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#define bfd_mach_m68040 6
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#define bfd_mach_m68060 7
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bfd_arch_vax, /* DEC Vax */
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bfd_arch_i960, /* Intel 960 */
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/* The order of the following is important.
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lower number indicates a machine type that
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only accepts a subset of the instructions
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available to machines with higher numbers.
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The exception is the "ca", which is
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incompatible with all other machines except
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"core". */
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#define bfd_mach_i960_core 1
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#define bfd_mach_i960_ka_sa 2
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#define bfd_mach_i960_kb_sb 3
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#define bfd_mach_i960_mc 4
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#define bfd_mach_i960_xa 5
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#define bfd_mach_i960_ca 6
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#define bfd_mach_i960_jx 7
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#define bfd_mach_i960_hx 8
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bfd_arch_a29k, /* AMD 29000 */
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bfd_arch_sparc, /* SPARC */
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#define bfd_mach_sparc 1
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/* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
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#define bfd_mach_sparc_sparclet 2
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#define bfd_mach_sparc_sparclite 3
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#define bfd_mach_sparc_v8plus 4
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#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns */
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#define bfd_mach_sparc_v9 6
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#define bfd_mach_sparc_v9a 7 /* with ultrasparc add'ns */
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/* Nonzero if MACH has the v9 instruction set. */
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#define bfd_mach_sparc_v9_p(mach) \
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((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a)
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bfd_arch_mips, /* MIPS Rxxxx */
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#define bfd_mach_mips3000 3000
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#define bfd_mach_mips3900 3900
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#define bfd_mach_mips4000 4000
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#define bfd_mach_mips4010 4010
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#define bfd_mach_mips4100 4100
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#define bfd_mach_mips4300 4300
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#define bfd_mach_mips4400 4400
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#define bfd_mach_mips4600 4600
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#define bfd_mach_mips4650 4650
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#define bfd_mach_mips5000 5000
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#define bfd_mach_mips6000 6000
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#define bfd_mach_mips8000 8000
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#define bfd_mach_mips10000 10000
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#define bfd_mach_mips16 16
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bfd_arch_i386, /* Intel 386 */
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#define bfd_mach_i386_i386 0
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#define bfd_mach_i386_i8086 1
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bfd_arch_we32k, /* AT&T WE32xxx */
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bfd_arch_tahoe, /* CCI/Harris Tahoe */
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bfd_arch_i860, /* Intel 860 */
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bfd_arch_romp, /* IBM ROMP PC/RT */
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bfd_arch_alliant, /* Alliant */
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bfd_arch_convex, /* Convex */
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bfd_arch_m88k, /* Motorola 88xxx */
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bfd_arch_pyramid, /* Pyramid Technology */
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bfd_arch_h8300, /* Hitachi H8/300 */
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#define bfd_mach_h8300 1
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#define bfd_mach_h8300h 2
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#define bfd_mach_h8300s 3
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bfd_arch_powerpc, /* PowerPC */
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bfd_arch_rs6000, /* IBM RS/6000 */
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bfd_arch_hppa, /* HP PA RISC */
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bfd_arch_d10v, /* Mitsubishi D10V */
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bfd_arch_z8k, /* Zilog Z8000 */
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#define bfd_mach_z8001 1
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#define bfd_mach_z8002 2
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bfd_arch_h8500, /* Hitachi H8/500 */
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bfd_arch_sh, /* Hitachi SH */
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#define bfd_mach_sh 0
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#define bfd_mach_sh3 0x30
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#define bfd_mach_sh3e 0x3e
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#define bfd_mach_sh4 0x40
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bfd_arch_alpha, /* Dec Alpha */
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bfd_arch_arm, /* Advanced Risc Machines ARM */
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#define bfd_mach_arm_2 1
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#define bfd_mach_arm_2a 2
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#define bfd_mach_arm_3 3
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#define bfd_mach_arm_3M 4
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#define bfd_mach_arm_4 5
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#define bfd_mach_arm_4T 6
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bfd_arch_ns32k, /* National Semiconductors ns32000 */
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bfd_arch_w65, /* WDC 65816 */
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bfd_arch_tic30, /* Texas Instruments TMS320C30 */
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bfd_arch_v850, /* NEC V850 */
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#define bfd_mach_v850 0
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bfd_arch_arc, /* Argonaut RISC Core */
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#define bfd_mach_arc_base 0
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bfd_arch_m32r, /* Mitsubishi M32R/D */
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#define bfd_mach_m32r 0 /* backwards compatibility */
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bfd_arch_mn10200, /* Matsushita MN10200 */
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bfd_arch_mn10300, /* Matsushita MN10300 */
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bfd_arch_last
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};
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typedef struct symbol_cache_entry
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{
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const char *name;
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union
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{
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PTR p;
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bfd_vma i;
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} udata;
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} asymbol;
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typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...));
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@ -176,8 +321,10 @@ extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*));
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#if 0
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/* Fetch the disassembler for a given BFD, if that support is available. */
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extern disassembler_ftype disassembler PARAMS ((bfd *));
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#endif
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/* This block of definitions is for particular callers who read instructions
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