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target/arm: Implement SVE2 integer multiply-add long

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-24 18:03:02 -07:00 committed by Peter Maydell
parent ab3ddf3185
commit 45a32e80b9
4 changed files with 133 additions and 0 deletions
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28
target/arm/helper-sve.h
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@ -2573,3 +2573,31 @@ DEF_HELPER_FLAGS_5(sve2_sqdmlsl_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlsl_zzzw_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_smlal_zzzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_smlal_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_smlal_zzzw_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_umlal_zzzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_umlal_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_umlal_zzzw_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_smlsl_zzzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_smlsl_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_smlsl_zzzw_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_umlsl_zzzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_umlsl_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_umlsl_zzzw_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)

11
target/arm/sve.decode
View File

@ -1351,3 +1351,14 @@ SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm
SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm
SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm
## SVE2 integer multiply-add long
SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm
SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm
UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm
UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm
SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm
SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm
UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm
UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm

18
target/arm/sve_helper.c
View File

@ -1313,6 +1313,24 @@ DO_ZZZW_ACC(sve2_uabal_h, uint16_t, uint8_t, H1_2, H1, DO_ABD)
DO_ZZZW_ACC(sve2_uabal_s, uint32_t, uint16_t, H1_4, H1_2, DO_ABD)
DO_ZZZW_ACC(sve2_uabal_d, uint64_t, uint32_t, , H1_4, DO_ABD)
DO_ZZZW_ACC(sve2_smlal_zzzw_h, int16_t, int8_t, H1_2, H1, DO_MUL)
DO_ZZZW_ACC(sve2_smlal_zzzw_s, int32_t, int16_t, H1_4, H1_2, DO_MUL)
DO_ZZZW_ACC(sve2_smlal_zzzw_d, int64_t, int32_t, , H1_4, DO_MUL)
DO_ZZZW_ACC(sve2_umlal_zzzw_h, uint16_t, uint8_t, H1_2, H1, DO_MUL)
DO_ZZZW_ACC(sve2_umlal_zzzw_s, uint32_t, uint16_t, H1_4, H1_2, DO_MUL)
DO_ZZZW_ACC(sve2_umlal_zzzw_d, uint64_t, uint32_t, , H1_4, DO_MUL)
#define DO_NMUL(N, M) -(N * M)
DO_ZZZW_ACC(sve2_smlsl_zzzw_h, int16_t, int8_t, H1_2, H1, DO_NMUL)
DO_ZZZW_ACC(sve2_smlsl_zzzw_s, int32_t, int16_t, H1_4, H1_2, DO_NMUL)
DO_ZZZW_ACC(sve2_smlsl_zzzw_d, int64_t, int32_t, , H1_4, DO_NMUL)
DO_ZZZW_ACC(sve2_umlsl_zzzw_h, uint16_t, uint8_t, H1_2, H1, DO_NMUL)
DO_ZZZW_ACC(sve2_umlsl_zzzw_s, uint32_t, uint16_t, H1_4, H1_2, DO_NMUL)
DO_ZZZW_ACC(sve2_umlsl_zzzw_d, uint64_t, uint32_t, , H1_4, DO_NMUL)
#undef DO_ZZZW_ACC
#define DO_XTNB(NAME, TYPE, OP) \

76
target/arm/translate-sve.c
View File

@ -7580,3 +7580,79 @@ static bool trans_SQRDMLSH_zzzz(DisasContext *s, arg_rrrr_esz *a)
};
return do_sve2_zzzz_ool(s, a, fns[a->esz], 0);
}
static bool do_smlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{
static gen_helper_gvec_4 * const fns[] = {
NULL, gen_helper_sve2_smlal_zzzw_h,
gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d,
};
return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
}
static bool trans_SMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_smlal_zzzw(s, a, false);
}
static bool trans_SMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_smlal_zzzw(s, a, true);
}
static bool do_umlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{
static gen_helper_gvec_4 * const fns[] = {
NULL, gen_helper_sve2_umlal_zzzw_h,
gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d,
};
return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
}
static bool trans_UMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_umlal_zzzw(s, a, false);
}
static bool trans_UMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_umlal_zzzw(s, a, true);
}
static bool do_smlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{
static gen_helper_gvec_4 * const fns[] = {
NULL, gen_helper_sve2_smlsl_zzzw_h,
gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d,
};
return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
}
static bool trans_SMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_smlsl_zzzw(s, a, false);
}
static bool trans_SMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_smlsl_zzzw(s, a, true);
}
static bool do_umlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{
static gen_helper_gvec_4 * const fns[] = {
NULL, gen_helper_sve2_umlsl_zzzw_h,
gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d,
};
return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
}
static bool trans_UMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_umlsl_zzzw(s, a, false);
}
static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_umlsl_zzzw(s, a, true);
}