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hw/nvram: Introduce Xilinx battery-backed ram
This device is present in Versal and ZynqMP product families to store a 256-bit encryption key. Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Tong Ho <tong.ho@xilinx.com> Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tong Ho
Peter Maydell
parent
67fa02f89f
commit
461a6a6f19
@ -30,3 +30,7 @@ config XLNX_EFUSE_VERSAL
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config XLNX_EFUSE_ZYNQMP
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bool
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select XLNX_EFUSE
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config XLNX_BBRAM
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bool
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select XLNX_EFUSE_CRC
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@ -16,5 +16,6 @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
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'xlnx-versal-efuse-ctrl.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
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'xlnx-zynqmp-efuse.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
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specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
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545
hw/nvram/xlnx-bbram.c
Normal file
545
hw/nvram/xlnx-bbram.c
Normal file
@ -0,0 +1,545 @@
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/*
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* QEMU model of the Xilinx BBRAM Battery Backed RAM
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*
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* Copyright (c) 2014-2021 Xilinx Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/nvram/xlnx-bbram.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "sysemu/blockdev.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/nvram/xlnx-efuse.h"
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#ifndef XLNX_BBRAM_ERR_DEBUG
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#define XLNX_BBRAM_ERR_DEBUG 0
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#endif
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REG32(BBRAM_STATUS, 0x0)
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FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1)
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FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1)
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FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1)
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FIELD(BBRAM_STATUS, PGM_MODE, 0, 1)
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REG32(BBRAM_CTRL, 0x4)
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FIELD(BBRAM_CTRL, ZEROIZE, 0, 1)
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REG32(PGM_MODE, 0x8)
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REG32(BBRAM_AES_CRC, 0xc)
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REG32(BBRAM_0, 0x10)
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REG32(BBRAM_1, 0x14)
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REG32(BBRAM_2, 0x18)
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REG32(BBRAM_3, 0x1c)
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REG32(BBRAM_4, 0x20)
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REG32(BBRAM_5, 0x24)
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REG32(BBRAM_6, 0x28)
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REG32(BBRAM_7, 0x2c)
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REG32(BBRAM_8, 0x30)
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REG32(BBRAM_SLVERR, 0x34)
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FIELD(BBRAM_SLVERR, ENABLE, 0, 1)
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REG32(BBRAM_ISR, 0x38)
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FIELD(BBRAM_ISR, APB_SLVERR, 0, 1)
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REG32(BBRAM_IMR, 0x3c)
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FIELD(BBRAM_IMR, APB_SLVERR, 0, 1)
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REG32(BBRAM_IER, 0x40)
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FIELD(BBRAM_IER, APB_SLVERR, 0, 1)
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REG32(BBRAM_IDR, 0x44)
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FIELD(BBRAM_IDR, APB_SLVERR, 0, 1)
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REG32(BBRAM_MSW_LOCK, 0x4c)
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FIELD(BBRAM_MSW_LOCK, VAL, 0, 1)
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#define R_MAX (R_BBRAM_MSW_LOCK + 1)
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#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
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#define BBRAM_PGM_MAGIC 0x757bdf0d
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QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
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static bool bbram_msw_locked(XlnxBBRam *s)
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{
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return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0;
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}
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static bool bbram_pgm_enabled(XlnxBBRam *s)
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{
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return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0;
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}
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static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
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{
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Error *errp;
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error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
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blk_name(s->blk), detail);
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error_report("%s", error_get_pretty(errp));
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error_free(errp);
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g_free(detail);
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}
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static void bbram_bdrv_read(XlnxBBRam *s, Error **errp)
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{
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uint32_t *ram = &s->regs[R_BBRAM_0];
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int nr = RAM_MAX;
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if (!s->blk) {
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return;
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}
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s->blk_ro = !blk_supports_write_perm(s->blk);
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if (!s->blk_ro) {
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int rc;
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rc = blk_set_perm(s->blk,
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(BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
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BLK_PERM_ALL, NULL);
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if (rc) {
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s->blk_ro = true;
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}
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}
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if (s->blk_ro) {
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warn_report("%s: Skip saving updates to read-only BBRAM backstore.",
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blk_name(s->blk));
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}
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if (blk_pread(s->blk, 0, ram, nr) < 0) {
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error_setg(errp,
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"%s: Failed to read %u bytes from BBRAM backstore.",
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blk_name(s->blk), nr);
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return;
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}
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/* Convert from little-endian backstore for each 32-bit word */
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nr /= 4;
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while (nr--) {
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ram[nr] = le32_to_cpu(ram[nr]);
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}
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}
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static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr)
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{
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uint32_t le32;
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unsigned offset;
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int rc;
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assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8);
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/* Backstore is always in little-endian */
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le32 = cpu_to_le32(s->regs[hwaddr / 4]);
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/* Update zeroized flag */
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if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) {
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ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0);
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}
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if (!s->blk || s->blk_ro) {
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return;
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}
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offset = hwaddr - A_BBRAM_0;
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rc = blk_pwrite(s->blk, offset, &le32, 4, 0);
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if (rc < 0) {
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bbram_bdrv_error(s, rc, g_strdup_printf("write to offset %u", offset));
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}
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}
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static void bbram_bdrv_zero(XlnxBBRam *s)
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{
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int rc;
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ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1);
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if (!s->blk || s->blk_ro) {
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return;
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}
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rc = blk_make_zero(s->blk, 0);
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if (rc < 0) {
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bbram_bdrv_error(s, rc, g_strdup("zeroizing"));
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}
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/* Restore bbram8 if it is non-zero */
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if (s->regs[R_BBRAM_8]) {
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bbram_bdrv_sync(s, A_BBRAM_8);
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}
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}
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static void bbram_zeroize(XlnxBBRam *s)
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{
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int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */
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memset(&s->regs[R_BBRAM_0], 0, nr);
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bbram_bdrv_zero(s);
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}
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static void bbram_update_irq(XlnxBBRam *s)
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{
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bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR];
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qemu_set_irq(s->irq_bbram, pending);
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}
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static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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uint32_t val = val64;
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if (val & R_BBRAM_CTRL_ZEROIZE_MASK) {
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bbram_zeroize(s);
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/* The bit is self clearing */
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s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK;
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}
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}
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static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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uint32_t val = val64;
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if (val == BBRAM_PGM_MAGIC) {
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bbram_zeroize(s);
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/* The status bit is cleared only by POR */
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ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1);
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}
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}
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static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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uint32_t calc_crc;
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if (!bbram_pgm_enabled(s)) {
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/* We are not in programming mode, don't do anything */
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return;
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}
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/* Perform the AES integrity check */
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s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK;
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/*
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* Set check status.
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*
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* ZynqMP BBRAM check has a zero-u32 prepended; see:
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* https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311
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*/
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calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0],
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(R_BBRAM_8 - R_BBRAM_0), s->crc_zpads);
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ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS,
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(s->regs[R_BBRAM_AES_CRC] == calc_crc));
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}
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static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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uint32_t original_data = *(uint32_t *) reg->data;
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if (bbram_pgm_enabled(s)) {
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return val64;
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} else {
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/* We are not in programming mode, don't do anything */
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qemu_log_mask(LOG_GUEST_ERROR,
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"Not in programming mode, dropping the write\n");
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return original_data;
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}
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}
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static void bbram_key_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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bbram_bdrv_sync(s, reg->access->addr);
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}
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static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val)
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{
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return 0;
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}
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static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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return s->bbram8_wo ? bbram_wo_postr(reg, val) : val;
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}
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static bool bbram_r8_readonly(XlnxBBRam *s)
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{
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return !bbram_pgm_enabled(s) || bbram_msw_locked(s);
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}
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static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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if (bbram_r8_readonly(s)) {
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val64 = *(uint32_t *)reg->data;
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}
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return val64;
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}
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static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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if (!bbram_r8_readonly(s)) {
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bbram_bdrv_sync(s, A_BBRAM_8);
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}
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}
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static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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/* Never lock if bbram8 is wo; and, only POR can clear the lock */
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if (s->bbram8_wo) {
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val64 = 0;
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} else {
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val64 |= s->regs[R_BBRAM_MSW_LOCK];
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}
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return val64;
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}
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static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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bbram_update_irq(s);
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}
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static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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uint32_t val = val64;
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s->regs[R_BBRAM_IMR] &= ~val;
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bbram_update_irq(s);
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return 0;
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}
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static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
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uint32_t val = val64;
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s->regs[R_BBRAM_IMR] |= val;
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bbram_update_irq(s);
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return 0;
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}
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static RegisterAccessInfo bbram_ctrl_regs_info[] = {
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{ .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS,
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.rsvd = 0xee,
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.ro = 0x3ff,
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},{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL,
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.post_write = bbram_ctrl_postw,
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},{ .name = "PGM_MODE", .addr = A_PGM_MODE,
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.post_write = bbram_pgm_mode_postw,
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},{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC,
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.post_write = bbram_aes_crc_postw,
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.post_read = bbram_wo_postr,
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},{ .name = "BBRAM_0", .addr = A_BBRAM_0,
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.pre_write = bbram_key_prew,
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.post_write = bbram_key_postw,
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.post_read = bbram_wo_postr,
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},{ .name = "BBRAM_1", .addr = A_BBRAM_1,
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.pre_write = bbram_key_prew,
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.post_write = bbram_key_postw,
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.post_read = bbram_wo_postr,
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},{ .name = "BBRAM_2", .addr = A_BBRAM_2,
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.pre_write = bbram_key_prew,
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.post_write = bbram_key_postw,
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.post_read = bbram_wo_postr,
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},{ .name = "BBRAM_3", .addr = A_BBRAM_3,
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.pre_write = bbram_key_prew,
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.post_write = bbram_key_postw,
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.post_read = bbram_wo_postr,
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},{ .name = "BBRAM_4", .addr = A_BBRAM_4,
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.pre_write = bbram_key_prew,
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.post_write = bbram_key_postw,
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.post_read = bbram_wo_postr,
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},{ .name = "BBRAM_5", .addr = A_BBRAM_5,
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.pre_write = bbram_key_prew,
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.post_write = bbram_key_postw,
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.post_read = bbram_wo_postr,
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},{ .name = "BBRAM_6", .addr = A_BBRAM_6,
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.pre_write = bbram_key_prew,
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.post_write = bbram_key_postw,
|
||||
.post_read = bbram_wo_postr,
|
||||
},{ .name = "BBRAM_7", .addr = A_BBRAM_7,
|
||||
.pre_write = bbram_key_prew,
|
||||
.post_write = bbram_key_postw,
|
||||
.post_read = bbram_wo_postr,
|
||||
},{ .name = "BBRAM_8", .addr = A_BBRAM_8,
|
||||
.pre_write = bbram_r8_prew,
|
||||
.post_write = bbram_r8_postw,
|
||||
.post_read = bbram_r8_postr,
|
||||
},{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR,
|
||||
.rsvd = ~1,
|
||||
},{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR,
|
||||
.w1c = 0x1,
|
||||
.post_write = bbram_isr_postw,
|
||||
},{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR,
|
||||
.ro = 0x1,
|
||||
},{ .name = "BBRAM_IER", .addr = A_BBRAM_IER,
|
||||
.pre_write = bbram_ier_prew,
|
||||
},{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR,
|
||||
.pre_write = bbram_idr_prew,
|
||||
},{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK,
|
||||
.pre_write = bbram_msw_lock_prew,
|
||||
.ro = ~R_BBRAM_MSW_LOCK_VAL_MASK,
|
||||
}
|
||||
};
|
||||
|
||||
static void bbram_ctrl_reset(DeviceState *dev)
|
||||
{
|
||||
XlnxBBRam *s = XLNX_BBRAM(dev);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
|
||||
if (i < R_BBRAM_0 || i > R_BBRAM_8) {
|
||||
register_reset(&s->regs_info[i]);
|
||||
}
|
||||
}
|
||||
|
||||
bbram_update_irq(s);
|
||||
}
|
||||
|
||||
static const MemoryRegionOps bbram_ctrl_ops = {
|
||||
.read = register_read_memory,
|
||||
.write = register_write_memory,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
};
|
||||
|
||||
static void bbram_ctrl_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
XlnxBBRam *s = XLNX_BBRAM(dev);
|
||||
|
||||
if (s->crc_zpads) {
|
||||
s->bbram8_wo = true;
|
||||
}
|
||||
|
||||
bbram_bdrv_read(s, errp);
|
||||
}
|
||||
|
||||
static void bbram_ctrl_init(Object *obj)
|
||||
{
|
||||
XlnxBBRam *s = XLNX_BBRAM(obj);
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||
RegisterInfoArray *reg_array;
|
||||
|
||||
reg_array =
|
||||
register_init_block32(DEVICE(obj), bbram_ctrl_regs_info,
|
||||
ARRAY_SIZE(bbram_ctrl_regs_info),
|
||||
s->regs_info, s->regs,
|
||||
&bbram_ctrl_ops,
|
||||
XLNX_BBRAM_ERR_DEBUG,
|
||||
R_MAX * 4);
|
||||
|
||||
sysbus_init_mmio(sbd, ®_array->mem);
|
||||
sysbus_init_irq(sbd, &s->irq_bbram);
|
||||
}
|
||||
|
||||
static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name,
|
||||
void *opaque, Error **errp)
|
||||
{
|
||||
DeviceState *dev = DEVICE(obj);
|
||||
|
||||
qdev_prop_drive.set(obj, v, name, opaque, errp);
|
||||
|
||||
/* Fill initial data if backend is attached after realized */
|
||||
if (dev->realized) {
|
||||
bbram_bdrv_read(XLNX_BBRAM(obj), errp);
|
||||
}
|
||||
}
|
||||
|
||||
static void bbram_prop_get_drive(Object *obj, Visitor *v, const char *name,
|
||||
void *opaque, Error **errp)
|
||||
{
|
||||
qdev_prop_drive.get(obj, v, name, opaque, errp);
|
||||
}
|
||||
|
||||
static void bbram_prop_release_drive(Object *obj, const char *name,
|
||||
void *opaque)
|
||||
{
|
||||
qdev_prop_drive.release(obj, name, opaque);
|
||||
}
|
||||
|
||||
static const PropertyInfo bbram_prop_drive = {
|
||||
.name = "str",
|
||||
.description = "Node name or ID of a block device to use as BBRAM backend",
|
||||
.realized_set_allowed = true,
|
||||
.get = bbram_prop_get_drive,
|
||||
.set = bbram_prop_set_drive,
|
||||
.release = bbram_prop_release_drive,
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_bbram_ctrl = {
|
||||
.name = TYPE_XLNX_BBRAM,
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
}
|
||||
};
|
||||
|
||||
static Property bbram_ctrl_props[] = {
|
||||
DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *),
|
||||
DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->reset = bbram_ctrl_reset;
|
||||
dc->realize = bbram_ctrl_realize;
|
||||
dc->vmsd = &vmstate_bbram_ctrl;
|
||||
device_class_set_props(dc, bbram_ctrl_props);
|
||||
}
|
||||
|
||||
static const TypeInfo bbram_ctrl_info = {
|
||||
.name = TYPE_XLNX_BBRAM,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(XlnxBBRam),
|
||||
.class_init = bbram_ctrl_class_init,
|
||||
.instance_init = bbram_ctrl_init,
|
||||
};
|
||||
|
||||
static void bbram_ctrl_register_types(void)
|
||||
{
|
||||
type_register_static(&bbram_ctrl_info);
|
||||
}
|
||||
|
||||
type_init(bbram_ctrl_register_types)
|
||||
54
include/hw/nvram/xlnx-bbram.h
Normal file
54
include/hw/nvram/xlnx-bbram.h
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* QEMU model of the Xilinx BBRAM Battery Backed RAM
|
||||
*
|
||||
* Copyright (c) 2015-2021 Xilinx Inc.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgari@xilinx.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#ifndef XLNX_BBRAM_H
|
||||
#define XLNX_BBRAM_H
|
||||
|
||||
#include "sysemu/block-backend.h"
|
||||
#include "hw/qdev-core.h"
|
||||
#include "hw/irq.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
|
||||
#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
|
||||
|
||||
#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
|
||||
|
||||
struct XlnxBBRam {
|
||||
SysBusDevice parent_obj;
|
||||
qemu_irq irq_bbram;
|
||||
|
||||
BlockBackend *blk;
|
||||
|
||||
uint32_t crc_zpads;
|
||||
bool bbram8_wo;
|
||||
bool blk_ro;
|
||||
|
||||
uint32_t regs[RMAX_XLNX_BBRAM];
|
||||
RegisterInfo regs_info[RMAX_XLNX_BBRAM];
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user