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Add a phy-num property to the i.MX FEC emulator
We need a solution to use an Ethernet PHY that is not the first device on the MDIO bus (device 0 on MDIO bus). As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but only one MDIO bus on which the 2 related PHY are connected but at unique addresses. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -280,12 +280,16 @@ static void imx_phy_reset(IMXFECState *s)
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static uint32_t imx_phy_read(IMXFECState *s, int reg)
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static uint32_t imx_phy_read(IMXFECState *s, int reg)
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{
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{
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uint32_t val;
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uint32_t val;
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uint32_t phy = reg / 32;
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if (reg > 31) {
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if (phy != s->phy_num) {
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/* we only advertise one phy */
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qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
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TYPE_IMX_FEC, __func__, phy);
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return 0;
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return 0;
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}
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}
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reg %= 32;
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switch (reg) {
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switch (reg) {
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case 0: /* Basic Control */
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case 0: /* Basic Control */
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val = s->phy_control;
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val = s->phy_control;
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@ -331,20 +335,25 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
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break;
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break;
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}
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}
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trace_imx_phy_read(val, reg);
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trace_imx_phy_read(val, phy, reg);
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return val;
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return val;
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}
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}
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static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
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static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
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{
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{
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trace_imx_phy_write(val, reg);
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uint32_t phy = reg / 32;
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if (reg > 31) {
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if (phy != s->phy_num) {
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/* we only advertise one phy */
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qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
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TYPE_IMX_FEC, __func__, phy);
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return;
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return;
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}
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}
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reg %= 32;
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trace_imx_phy_write(val, phy, reg);
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switch (reg) {
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switch (reg) {
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case 0: /* Basic Control */
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case 0: /* Basic Control */
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if (val & 0x8000) {
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if (val & 0x8000) {
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@ -926,7 +935,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
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extract32(value,
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extract32(value,
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18, 10)));
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18, 10)));
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} else {
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} else {
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/* This a write operation */
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/* This is a write operation */
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imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
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imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
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}
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}
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/* raise the interrupt as the PHY operation is done */
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/* raise the interrupt as the PHY operation is done */
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@ -1315,6 +1324,7 @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
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static Property imx_eth_properties[] = {
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static Property imx_eth_properties[] = {
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DEFINE_NIC_PROPERTIES(IMXFECState, conf),
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DEFINE_NIC_PROPERTIES(IMXFECState, conf),
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DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
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DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
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DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -413,8 +413,8 @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
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i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
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i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
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# imx_fec.c
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# imx_fec.c
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imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
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imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
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imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
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imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
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imx_phy_update_link(const char *s) "%s"
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imx_phy_update_link(const char *s) "%s"
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imx_phy_reset(void) ""
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imx_phy_reset(void) ""
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imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
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imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
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@ -268,6 +268,7 @@ typedef struct IMXFECState {
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uint32_t phy_advertise;
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uint32_t phy_advertise;
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uint32_t phy_int;
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uint32_t phy_int;
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uint32_t phy_int_mask;
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uint32_t phy_int_mask;
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uint32_t phy_num;
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bool is_fec;
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bool is_fec;
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