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s390x/tcg: Define vector instruction formats
These are the new instruction formats related to vector instructions as up to the z14 (a.k.a. latest PoP). As v2 appeares (like x2 in VRX) with d2/b2 in VRV, we have to assign it a higher field number to avoid collisions. Properly take care of the MSB (to be able to address 32 registers) for each vector register field stored in the RXB field (Bit 36 - 30 for all vector instructions). As we have 32 bit vector registers and the "v" fields are only 4 bit in size, the 5th bit is stored in the RXB. We use a new type to indicate that the MSB has to be fetched from the RXB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
David Hildenbrand
Cornelia Huck
parent
a5f5ca5eaf
commit
481accd4f5
@ -54,3 +54,28 @@ F4(SS_e, R(1, 8), BD(2,16,20), R(3,12), BD(4,32,36))
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F3(SS_f, BD(1,16,20), L(2,8,8), BD(2,32,36))
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F2(SSE, BD(1,16,20), BD(2,32,36))
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F3(SSF, BD(1,16,20), BD(2,32,36), R(3,8))
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F3(VRI_a, V(1,8), I(2,16,16), M(3,32))
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F4(VRI_b, V(1,8), I(2,16,8), I(3,24,8), M(4,32))
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F4(VRI_c, V(1,8), V(3,12), I(2,16,16), M(4,32))
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F5(VRI_d, V(1,8), V(2,12), V(3,16), I(4,24,8), M(5,32))
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F5(VRI_e, V(1,8), V(2,12), I(3,16,12), M(5,28), M(4,32))
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F5(VRI_f, V(1,8), V(2,12), V(3,16), M(5,24), I(4,28,8))
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F5(VRI_g, V(1,8), V(2,12), I(4,16,8), M(5,24), I(3,28,8))
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F3(VRI_h, V(1,8), I(2,16,16), I(3,32,4))
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F4(VRI_i, V(1,8), R(2,12), M(4,24), I(3,28,8))
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F5(VRR_a, V(1,8), V(2,12), M(5,24), M(4,28), M(3,32))
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F5(VRR_b, V(1,8), V(2,12), V(3,16), M(5,24), M(4,32))
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F6(VRR_c, V(1,8), V(2,12), V(3,16), M(6,24), M(5,28), M(4,32))
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F6(VRR_d, V(1,8), V(2,12), V(3,16), M(5,20), M(6,24), V(4,32))
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F6(VRR_e, V(1,8), V(2,12), V(3,16), M(6,20), M(5,28), V(4,32))
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F3(VRR_f, V(1,8), R(2,12), R(3,16))
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F1(VRR_g, V(1,12))
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F3(VRR_h, V(1,12), V(2,16), M(3,24))
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F3(VRR_i, R(1,8), V(2,12), M(3,24))
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F4(VRS_a, V(1,8), V(3,12), BD(2,16,20), M(4,32))
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F4(VRS_b, V(1,8), R(3,12), BD(2,16,20), M(4,32))
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F4(VRS_c, R(1,8), V(3,12), BD(2,16,20), M(4,32))
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F3(VRS_d, R(3,12), BD(2,16,20), V(1,32))
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F4(VRV, V(1,8), V(2,12), BD(2,16,20), M(3,32))
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F3(VRX, V(1,8), BXD(2), M(3,32))
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F3(VSI, I(3,8,8), BD(2,16,20), V(1,32))
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@ -985,6 +985,7 @@ static void free_compare(DisasCompare *c)
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#define F3(N, X1, X2, X3) F0(N)
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#define F4(N, X1, X2, X3, X4) F0(N)
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#define F5(N, X1, X2, X3, X4, X5) F0(N)
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#define F6(N, X1, X2, X3, X4, X5, X6) F0(N)
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typedef enum {
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#include "insn-format.def"
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@ -996,6 +997,7 @@ typedef enum {
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#undef F3
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#undef F4
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#undef F5
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#undef F6
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/* Define a structure to hold the decoded fields. We'll store each inside
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an array indexed by an enum. In order to conserve memory, we'll arrange
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@ -1010,6 +1012,8 @@ enum DisasFieldIndexO {
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FLD_O_m1,
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FLD_O_m3,
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FLD_O_m4,
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FLD_O_m5,
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FLD_O_m6,
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FLD_O_b1,
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FLD_O_b2,
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FLD_O_b4,
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@ -1023,7 +1027,11 @@ enum DisasFieldIndexO {
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FLD_O_i2,
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FLD_O_i3,
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FLD_O_i4,
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FLD_O_i5
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FLD_O_i5,
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FLD_O_v1,
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FLD_O_v2,
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FLD_O_v3,
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FLD_O_v4,
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};
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enum DisasFieldIndexC {
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@ -1031,6 +1039,7 @@ enum DisasFieldIndexC {
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FLD_C_m1 = 0,
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FLD_C_b1 = 0,
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FLD_C_i1 = 0,
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FLD_C_v1 = 0,
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FLD_C_r2 = 1,
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FLD_C_b2 = 1,
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@ -1039,20 +1048,25 @@ enum DisasFieldIndexC {
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FLD_C_r3 = 2,
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FLD_C_m3 = 2,
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FLD_C_i3 = 2,
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FLD_C_v3 = 2,
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FLD_C_m4 = 3,
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FLD_C_b4 = 3,
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FLD_C_i4 = 3,
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FLD_C_l1 = 3,
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FLD_C_v4 = 3,
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FLD_C_i5 = 4,
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FLD_C_d1 = 4,
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FLD_C_m5 = 4,
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FLD_C_d2 = 5,
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FLD_C_m6 = 5,
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FLD_C_d4 = 6,
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FLD_C_x2 = 6,
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FLD_C_l2 = 6,
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FLD_C_v2 = 6,
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NUM_C_FIELD = 7
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};
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@ -1097,6 +1111,7 @@ typedef struct DisasFormatInfo {
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#define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
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#define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
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#define V(N, B) { B, 4, 3, FLD_C_v##N, FLD_O_v##N }
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#define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
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{ BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
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#define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
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@ -1116,6 +1131,7 @@ typedef struct DisasFormatInfo {
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#define F3(N, X1, X2, X3) { { X1, X2, X3 } },
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#define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
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#define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
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#define F6(N, X1, X2, X3, X4, X5, X6) { { X1, X2, X3, X4, X5, X6 } },
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static const DisasFormatInfo format_info[] = {
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#include "insn-format.def"
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@ -1127,8 +1143,10 @@ static const DisasFormatInfo format_info[] = {
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#undef F3
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#undef F4
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#undef F5
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#undef F6
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#undef R
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#undef M
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#undef V
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#undef BD
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#undef BXD
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#undef BDL
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@ -6119,6 +6137,25 @@ static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
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case 2: /* dl+dh split, signed 20 bit. */
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r = ((int8_t)r << 12) | (r >> 8);
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break;
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case 3: /* MSB stored in RXB */
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g_assert(f->size == 4);
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switch (f->beg) {
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case 8:
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r |= extract64(insn, 63 - 36, 1) << 4;
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break;
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case 12:
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r |= extract64(insn, 63 - 37, 1) << 4;
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break;
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case 16:
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r |= extract64(insn, 63 - 38, 1) << 4;
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break;
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case 32:
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r |= extract64(insn, 63 - 39, 1) << 4;
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break;
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default:
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g_assert_not_reached();
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}
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break;
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default:
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abort();
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}
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