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hw: remove error handling from qemu_malloc() callers (Avi Kivity)

Browse Source 
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6529 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori 2009-02-05 22:06:05 +00:00
parent 090f1fa323
commit 487414f1cb
74 changed files with 257 additions and 545 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/adlib.c
View File

@ -331,13 +331,6 @@ int Adlib_init (AudioState *audio, qemu_irq *pic)
s->samples = AUD_get_buffer_size_out (s->voice) >> SHIFT;
s->mixbuf = qemu_mallocz (s->samples << SHIFT);
if (!s->mixbuf) {
dolog ("Could not allocate mixing buffer, %d samples (each %d bytes)\n",
s->samples, 1 << SHIFT);
Adlib_fini (s);
return -1;
}
register_ioport_read (0x388, 4, 1, adlib_read, s);
register_ioport_write (0x388, 4, 1, adlib_write, s);

4
hw/apic.c
View File

@ -898,8 +898,6 @@ int apic_init(CPUState *env)
if (last_apic_id >= MAX_APICS)
return -1;
s = qemu_mallocz(sizeof(APICState));
if (!s)
return -1;
env->apic_state = s;
s->id = last_apic_id++;
env->cpuid_apic_id = s->id;
@ -1124,8 +1122,6 @@ IOAPICState *ioapic_init(void)
int io_memory;
s = qemu_mallocz(sizeof(IOAPICState));
if (!s)
return NULL;
ioapic_reset(s);
s->id = last_apic_id++;

2
hw/arm_gic.c
View File

@ -725,8 +725,6 @@ static gic_state *gic_init(uint32_t dist_base, qemu_irq *parent_irq)
int i;
s = (gic_state *)qemu_mallocz(sizeof(gic_state));
if (!s)
return NULL;
s->in = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ);
for (i = 0; i < NCPU; i++) {
s->parent_irq[i] = parent_irq[i];

2
hw/arm_sysctl.c
View File

@ -194,8 +194,6 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id)
int iomemtype;
s = (arm_sysctl_state *)qemu_mallocz(sizeof(arm_sysctl_state));
if (!s)
return;
s->sys_id = sys_id;
/* The MPcore bootloader uses these flags to start secondary CPUs.
We don't use a bootloader, so do this here. */

10
hw/baum.c
View File

@ -575,12 +575,7 @@ CharDriverState *chr_baum_init(void)
int tty;
baum = qemu_mallocz(sizeof(BaumDriverState));
if (!baum)
return NULL;
baum->chr = chr = qemu_mallocz(sizeof(CharDriverState));
if (!chr)
goto fail_baum;
chr->opaque = baum;
chr->chr_write = baum_write;
@ -588,8 +583,6 @@ CharDriverState *chr_baum_init(void)
chr->chr_accept_input = baum_accept_input;
handle = qemu_mallocz(brlapi_getHandleSize());
if (!handle)
goto fail_chr;
baum->brlapi = handle;
baum->brlapi_fd = brlapi__openConnection(handle, NULL, NULL);
@ -628,11 +621,8 @@ CharDriverState *chr_baum_init(void)
fail:
qemu_free_timer(baum->cellCount_timer);
brlapi__closeConnection(handle);
fail_handle:
free(handle);
fail_chr:
free(chr);
fail_baum:
free(baum);
return NULL;
}

2
hw/cs4231.c
View File

@ -171,8 +171,6 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
CSState *s;
s = qemu_mallocz(sizeof(CSState));
if (!s)
return;
cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);

5
hw/cs4231a.c
View File

@ -647,11 +647,6 @@ int cs4231a_init (AudioState *audio, qemu_irq *pic)
}
s = qemu_mallocz (sizeof (*s));
if (!s) {
lerr ("Could not allocate memory for cs4231a (%zu bytes)\n",
sizeof (*s));
return -1;
}
s->pic = pic;
s->irq = conf.irq;

5
hw/ds1225y.c
View File

@ -152,13 +152,8 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
QEMUFile *file;
s = qemu_mallocz(sizeof(ds1225y_t));
if (!s)
return NULL;
s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
s->contents = qemu_mallocz(s->chip_size);
if (!s->contents) {
return NULL;
}
s->protection = 7;
/* Read current file */

2
hw/eccmemctl.c
View File

@ -320,8 +320,6 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
ECCState *s;
s = qemu_mallocz(sizeof(ECCState));
if (!s)
return NULL;
s->version = version;
s->regs[0] = version;

4
hw/escc.c
View File

@ -727,8 +727,6 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
SerialState *s;
s = qemu_mallocz(sizeof(SerialState));
if (!s)
return 0;
escc_io_memory = cpu_register_io_memory(0, escc_mem_read,
escc_mem_write,
@ -909,8 +907,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
SerialState *s;
s = qemu_mallocz(sizeof(SerialState));
if (!s)
return;
s->it_shift = it_shift;
for (i = 0; i < 2; i++) {

2
hw/esp.c
View File

@ -653,8 +653,6 @@ void *esp_init(target_phys_addr_t espaddr, int it_shift,
int esp_io_memory;
s = qemu_mallocz(sizeof(ESPState));
if (!s)
return NULL;
s->irq = irq;
s->it_shift = it_shift;

8
hw/etraxfs_dma.c
View File

@ -756,22 +756,14 @@ void *etraxfs_dmac_init(CPUState *env,
struct fs_dma_ctrl *ctrl = NULL;
ctrl = qemu_mallocz(sizeof *ctrl);
if (!ctrl)
return NULL;
ctrl->bh = qemu_bh_new(DMA_run, ctrl);
ctrl->env = env;
ctrl->nr_channels = nr_channels;
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
if (!ctrl->channels)
goto err;
ctrl->map = cpu_register_io_memory(0, dma_read, dma_write, ctrl);
cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
return ctrl;
err:
qemu_free(ctrl->channels);
qemu_free(ctrl);
return NULL;
}

8
hw/etraxfs_eth.c
View File

@ -564,12 +564,8 @@ void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
qemu_check_nic_model(nd, "fseth");
dma = qemu_mallocz(sizeof *dma * 2);
if (!dma)
return NULL;
eth = qemu_mallocz(sizeof *eth);
if (!eth)
goto err;
dma[0].client.push = eth_tx_push;
dma[0].client.opaque = eth;
@ -595,8 +591,4 @@ void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
eth->vc->link_status_changed = eth_set_link;
return dma;
err:
qemu_free(eth);
qemu_free(dma);
return NULL;
}

6
hw/etraxfs_pic.c
View File

@ -192,8 +192,6 @@ struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
pic = qemu_mallocz(sizeof *pic);
pic->internal = fs = qemu_mallocz(sizeof *fs);
if (!fs || !pic)
goto err;
fs->env = env;
pic->irq = qemu_allocate_irqs(irq_handler, fs, 30);
@ -204,8 +202,4 @@ struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
cpu_register_physical_memory(base, 0x14, intr_vect_regs);
return pic;
err:
free(pic);
free(fs);
return NULL;
}

2
hw/etraxfs_ser.c
View File

@ -233,8 +233,6 @@ void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
int ser_regs;
s = qemu_mallocz(sizeof *s);
if (!s)
return;
s->env = env;
s->irq = irq;

2
hw/etraxfs_timer.c
View File

@ -321,8 +321,6 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
int timer_regs;
t = qemu_mallocz(sizeof *t);
if (!t)
return;
t->bh_t0 = qemu_bh_new(timer0_hit, t);
t->bh_t1 = qemu_bh_new(timer1_hit, t);

6
hw/fdc.c
View File

@ -1866,13 +1866,7 @@ static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
FLOPPY_DPRINTF("init controller\n");
fdctrl = qemu_mallocz(sizeof(fdctrl_t));
if (!fdctrl)
return NULL;
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
if (fdctrl->fifo == NULL) {
qemu_free(fdctrl);
return NULL;
}
fdctrl->result_timer = qemu_new_timer(vm_clock,
fdctrl_result_timer, fdctrl);

27
hw/fmopl.c
View File

@ -619,26 +619,10 @@ static int OPLOpenTable( void )
double pom;
/* allocate dynamic tables */
if( (TL_TABLE = malloc(TL_MAX*2*sizeof(INT32))) == NULL)
return 0;
if( (SIN_TABLE = malloc(SIN_ENT*4 *sizeof(INT32 *))) == NULL)
{
free(TL_TABLE);
return 0;
}
if( (AMS_TABLE = malloc(AMS_ENT*2 *sizeof(INT32))) == NULL)
{
free(TL_TABLE);
free(SIN_TABLE);
return 0;
}
if( (VIB_TABLE = malloc(VIB_ENT*2 *sizeof(INT32))) == NULL)
{
free(TL_TABLE);
free(SIN_TABLE);
free(AMS_TABLE);
return 0;
}
TL_TABLE = qemu_malloc(TL_MAX*2*sizeof(INT32));
SIN_TABLE = qemu_malloc(SIN_ENT*4 *sizeof(INT32 *));
AMS_TABLE = qemu_malloc(AMS_ENT*2 *sizeof(INT32));
VIB_TABLE = qemu_malloc(VIB_ENT*2 *sizeof(INT32));
/* make total level table */
for (t = 0;t < EG_ENT-1 ;t++){
rate = ((1<<TL_BITS)-1)/pow(10,EG_STEP*t/20); /* dB -> voltage */
@ -1221,8 +1205,7 @@ FM_OPL *OPLCreate(int type, int clock, int rate)
if(type&OPL_TYPE_ADPCM) state_size+= sizeof(YM_DELTAT);
#endif
/* allocate memory block */
ptr = malloc(state_size);
if(ptr==NULL) return NULL;
ptr = qemu_malloc(state_size);
/* clear */
memset(ptr,0,state_size);
OPL = (FM_OPL *)ptr; ptr+=sizeof(FM_OPL);

8
hw/fw_cfg.c
View File

@ -206,8 +206,6 @@ int fw_cfg_add_i16(void *opaque, uint16_t key, uint16_t value)
uint16_t *copy;
copy = qemu_malloc(sizeof(value));
if (!copy)
return 0;
*copy = cpu_to_le16(value);
return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
}
@ -217,8 +215,6 @@ int fw_cfg_add_i32(void *opaque, uint16_t key, uint32_t value)
uint32_t *copy;
copy = qemu_malloc(sizeof(value));
if (!copy)
return 0;
*copy = cpu_to_le32(value);
return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
}
@ -228,8 +224,6 @@ int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value)
uint64_t *copy;
copy = qemu_malloc(sizeof(value));
if (!copy)
return 0;
*copy = cpu_to_le64(value);
return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
}
@ -263,8 +257,6 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
int io_ctl_memory, io_data_memory;
s = qemu_mallocz(sizeof(FWCfgState));
if (!s)
return NULL;
if (ctl_port) {
register_ioport_write(ctl_port, 2, 2, fw_cfg_io_writew, s);

2
hw/g364fb.c
View File

@ -593,8 +593,6 @@ int g364fb_mm_init(uint8_t *vram, ram_addr_t vram_offset,
int io_ctrl;
s = qemu_mallocz(sizeof(G364State));
if (!s)
return -1;
s->vram = vram;
s->vram_offset = vram_offset;

11
hw/gus.c
View File

@ -261,11 +261,6 @@ int GUS_init (AudioState *audio, qemu_irq *pic)
}
s = qemu_mallocz (sizeof (*s));
if (!s) {
dolog ("Could not allocate memory for GUS (%zu bytes)\n",
sizeof (*s));
return -1;
}
AUD_register_card (audio, "gus", &s->card);
@ -292,12 +287,6 @@ int GUS_init (AudioState *audio, qemu_irq *pic)
s->shift = 2;
s->samples = AUD_get_buffer_size_out (s->voice) >> s->shift;
s->mixbuf = qemu_mallocz (s->samples << s->shift);
if (!s->mixbuf) {
AUD_close_out (&s->card, s->voice);
AUD_remove_card (&s->card);
qemu_free (s);
return -1;
}
register_ioport_write (conf.port, 1, 1, gus_writeb, s);
register_ioport_write (conf.port, 1, 2, gus_writew, s);

2
hw/i8259.c
View File

@ -550,8 +550,6 @@ qemu_irq *i8259_init(qemu_irq parent_irq)
PicState2 *s;
s = qemu_mallocz(sizeof(PicState2));
if (!s)
return NULL;
pic_init1(0x20, 0x4d0, &s->pics[0]);
pic_init1(0xa0, 0x4d1, &s->pics[1]);
s->pics[0].elcr_mask = 0xf8;

2
hw/ide.c
View File

@ -2895,8 +2895,6 @@ void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
IDEState *ide_state;
ide_state = qemu_mallocz(sizeof(IDEState) * 2);
if (!ide_state)
return;
ide_init2(ide_state, hd0, hd1, irq);
ide_init_ioport(ide_state, iobase, iobase2);

2
hw/integratorcp.c
View File

@ -378,8 +378,6 @@ static qemu_irq *icp_pic_init(uint32_t base,
qemu_irq *qi;
s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
if (!s)
return NULL;
qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);
s->parent_irq = parent_irq;
s->parent_fiq = parent_fiq;

2
hw/iommu.c
View File

@ -371,8 +371,6 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
int iommu_io_memory;
s = qemu_mallocz(sizeof(IOMMUState));
if (!s)
return NULL;
s->version = version;
s->irq = irq;

2
hw/jazz_led.c
View File

@ -304,8 +304,6 @@ void jazz_led_init(target_phys_addr_t base)
int io;
s = qemu_mallocz(sizeof(LedState));
if (!s)
return;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;

6
hw/m48t59.c
View File

@ -622,13 +622,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
target_phys_addr_t save_base;
s = qemu_mallocz(sizeof(m48t59_t));
if (!s)
return NULL;
s->buffer = qemu_mallocz(size);
if (!s->buffer) {
qemu_free(s);
return NULL;
}
s->IRQ = IRQ;
s->size = size;
s->io_base = io_base;

2
hw/mac_dbdma.c
View File

@ -865,8 +865,6 @@ void* DBDMA_init (int *dbdma_mem_index)
DBDMA_channel *s;
s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
if (!s)
return NULL;
*dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);

6
hw/mac_nvram.c
View File

@ -132,13 +132,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
MacIONVRAMState *s;
s = qemu_mallocz(sizeof(MacIONVRAMState));
if (!s)
return NULL;
s->data = qemu_mallocz(size);
if (!s->data) {
qemu_free(s);
return NULL;
}
s->size = size;
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);

4
hw/mc146818rtc.c
View File

@ -532,8 +532,6 @@ RTCState *rtc_init(int base, qemu_irq irq, int base_year)
RTCState *s;
s = qemu_mallocz(sizeof(RTCState));
if (!s)
return NULL;
s->irq = irq;
s->cmos_data[RTC_REG_A] = 0x26;
@ -644,8 +642,6 @@ RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
int io_memory;
s = qemu_mallocz(sizeof(RTCState));
if (!s)
return NULL;
s->irq = irq;
s->cmos_data[RTC_REG_A] = 0x26;

2
hw/mipsnet.c
View File

@ -239,8 +239,6 @@ void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
qemu_check_nic_model(nd, "mipsnet");
s = qemu_mallocz(sizeof(MIPSnetState));
if (!s)
return;
register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);

2
hw/mpcore.c
View File

@ -265,8 +265,6 @@ static qemu_irq *mpcore_priv_init(uint32_t base, qemu_irq *pic_irq)
int i;
s = (mpcore_priv_state *)qemu_mallocz(sizeof(mpcore_priv_state));
if (!s)
return NULL;
s->gic = gic_init(base + 0x1000, pic_irq);
if (!s->gic)
return NULL;

2
hw/mst_fpga.c
View File

@ -225,8 +225,6 @@ qemu_irq *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq)
s = (mst_irq_state *)
qemu_mallocz(sizeof(mst_irq_state));
if (!s)
return NULL;
s->parent = &cpu->pic[irq];
/* alloc the external 16 irqs */

14
hw/musicpal.c
View File

@ -443,13 +443,9 @@ static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
}
s = qemu_mallocz(sizeof(musicpal_audio_state));
if (!s)
return NULL;
s->irq = irq;
i2c = qemu_mallocz(sizeof(i2c_interface));
if (!i2c)
return NULL;
i2c->bus = i2c_init_bus();
i2c->current_addr = -1;
@ -717,8 +713,6 @@ static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
qemu_check_nic_model(nd, "mv88w8618");
s = qemu_mallocz(sizeof(mv88w8618_eth_state));
if (!s)
return;
s->irq = irq;
s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
eth_receive, eth_can_receive, s);
@ -911,8 +905,6 @@ static void musicpal_lcd_init(uint32_t base)
int iomemtype;
s = qemu_mallocz(sizeof(musicpal_lcd_state));
if (!s)
return;
iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
musicpal_lcd_writefn, s);
cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
@ -1008,8 +1000,6 @@ static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
qemu_irq *qi;
s = qemu_mallocz(sizeof(mv88w8618_pic_state));
if (!s)
return NULL;
qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
s->parent_irq = parent_irq;
iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
@ -1134,8 +1124,6 @@ static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
mv88w8618_pit_state *s;
s = qemu_mallocz(sizeof(mv88w8618_pit_state));
if (!s)
return;
/* Letting them all run at 1 MHz is likely just a pragmatic
* simplification. */
@ -1200,8 +1188,6 @@ static void mv88w8618_flashcfg_init(uint32_t base)
mv88w8618_flashcfg_state *s;
s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
if (!s)
return;
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,

2
hw/ne2000.c
View File

@ -725,8 +725,6 @@ void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
qemu_check_nic_model(nd, "ne2k_isa");
s = qemu_mallocz(sizeof(NE2000State));
if (!s)
return;
register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
register_ioport_read(base, 16, 1, ne2000_ioport_read, s);

4
hw/parallel.c
View File

@ -445,8 +445,6 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
uint8_t dummy;
s = qemu_mallocz(sizeof(ParallelState));
if (!s)
return NULL;
s->irq = irq;
s->chr = chr;
parallel_reset(s);
@ -539,8 +537,6 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
int io_sw;
s = qemu_mallocz(sizeof(ParallelState));
if (!s)
return NULL;
s->irq = irq;
s->chr = chr;
s->it_shift = it_shift;

2
hw/pci.c
View File

@ -178,8 +178,6 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name,
found: ;
}
pci_dev = qemu_mallocz(instance_size);
if (!pci_dev)
return NULL;
pci_dev->bus = bus;
pci_dev->devfn = devfn;
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);

2
hw/pcnet.c
View File

@ -2089,8 +2089,6 @@ void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
qemu_check_nic_model(nd, "lance");
d = qemu_mallocz(sizeof(PCNetState));
if (!d)
return;
lance_io_memory =
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);

2
hw/pflash_cfi01.c
View File

@ -519,8 +519,6 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
pfl = qemu_mallocz(sizeof(pflash_t));
if (pfl == NULL)
return NULL;
pfl->storage = phys_ram_base + off;
pfl->fl_mem = cpu_register_io_memory(0,
pflash_read_ops, pflash_write_ops, pfl);

2
hw/pflash_cfi02.c
View File

@ -557,8 +557,6 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
return NULL;
#endif
pfl = qemu_mallocz(sizeof(pflash_t));
if (pfl == NULL)
return NULL;
pfl->storage = phys_ram_base + off;
pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
pfl);

2
hw/pl031.c
View File

@ -193,8 +193,6 @@ void pl031_init(uint32_t base, qemu_irq irq)
struct tm tm;
s = qemu_mallocz(sizeof(pl031_state));
if (!s)
cpu_abort(cpu_single_env, "pl031_init: Out of memory\n");
iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
if (iomemtype == -1)

7
hw/ppc.c
View File

@ -645,8 +645,6 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
ppc_tb_t *tb_env;
tb_env = qemu_mallocz(sizeof(ppc_tb_t));
if (tb_env == NULL)
return NULL;
env->tb_env = tb_env;
/* Create new timer */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
@ -915,9 +913,6 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
ppcemb_timer_t *ppcemb_timer;
tb_env = qemu_mallocz(sizeof(ppc_tb_t));
if (tb_env == NULL) {
return NULL;
}
env->tb_env = tb_env;
ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
tb_env->tb_freq = freq;
@ -1024,8 +1019,6 @@ int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
ppc_dcr_t *dcr_env;
dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
if (dcr_env == NULL)
return -1;
dcr_env->read_error = read_error;
dcr_env->write_error = write_error;
env->dcr_env = dcr_env;

24
hw/ppc405_boards.c
View File

@ -162,13 +162,11 @@ static void ref405ep_fpga_init (uint32_t base)
int fpga_memory;
fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
if (fpga != NULL) {
fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
ref405ep_fpga_reset(fpga);
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
ref405ep_fpga_reset(fpga);
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
@ -486,13 +484,11 @@ static void taihu_cpld_init (uint32_t base)
int cpld_memory;
cpld = qemu_mallocz(sizeof(taihu_cpld_t));
if (cpld != NULL) {
cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
taihu_cpld_write, cpld);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
taihu_cpld_reset(cpld);
qemu_register_reset(&taihu_cpld_reset, cpld);
}
cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
taihu_cpld_write, cpld);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
taihu_cpld_reset(cpld);
qemu_register_reset(&taihu_cpld_reset, cpld);
}
static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,

422
hw/ppc405_uc.c
View File

@ -169,13 +169,11 @@ void ppc4xx_plb_init (CPUState *env)
ppc4xx_plb_t *plb;
plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
if (plb != NULL) {
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_plb_reset(plb);
qemu_register_reset(ppc4xx_plb_reset, plb);
}
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_plb_reset(plb);
qemu_register_reset(ppc4xx_plb_reset, plb);
}
/*****************************************************************************/
@ -248,13 +246,11 @@ void ppc4xx_pob_init (CPUState *env)
ppc4xx_pob_t *pob;
pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
if (pob != NULL) {
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
qemu_register_reset(ppc4xx_pob_reset, pob);
ppc4xx_pob_reset(env);
}
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
qemu_register_reset(ppc4xx_pob_reset, pob);
ppc4xx_pob_reset(env);
}
/*****************************************************************************/
@ -384,16 +380,14 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
ppc4xx_opba_t *opba;
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
if (opba != NULL) {
opba->base = offset;
opba->base = offset;
#ifdef DEBUG_OPBA
printf("%s: offset " PADDRX "\n", __func__, offset);
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x002,
opba_read, opba_write, opba);
qemu_register_reset(ppc4xx_opba_reset, opba);
ppc4xx_opba_reset(opba);
}
ppc4xx_mmio_register(env, mmio, offset, 0x002,
opba_read, opba_write, opba);
qemu_register_reset(ppc4xx_opba_reset, opba);
ppc4xx_opba_reset(opba);
}
/*****************************************************************************/
@ -585,14 +579,12 @@ void ppc405_ebc_init (CPUState *env)
ppc4xx_ebc_t *ebc;
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
if (ebc != NULL) {
ebc_reset(ebc);
qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc_dcr_register(env, EBC0_CFGDATA,
ebc, &dcr_read_ebc, &dcr_write_ebc);
}
ebc_reset(ebc);
qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc_dcr_register(env, EBC0_CFGDATA,
ebc, &dcr_read_ebc, &dcr_write_ebc);
}
/*****************************************************************************/
@ -678,59 +670,57 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
ppc405_dma_t *dma;
dma = qemu_mallocz(sizeof(ppc405_dma_t));
if (dma != NULL) {
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
ppc405_dma_reset(dma);
qemu_register_reset(&ppc405_dma_reset, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CR1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CR2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CR3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SR,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SGC,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SLP,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_POL,
dma, &dcr_read_dma, &dcr_write_dma);
}
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
ppc405_dma_reset(dma);
qemu_register_reset(&ppc405_dma_reset, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CR1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG1,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CR2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG2,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CR3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_DA3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SA3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SG3,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SR,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SGC,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_SLP,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_POL,
dma, &dcr_read_dma, &dcr_write_dma);
}
/*****************************************************************************/
@ -845,16 +835,14 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
ppc405_gpio_t *gpio;
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
if (gpio != NULL) {
gpio->base = offset;
ppc405_gpio_reset(gpio);
qemu_register_reset(&ppc405_gpio_reset, gpio);
gpio->base = offset;
ppc405_gpio_reset(gpio);
qemu_register_reset(&ppc405_gpio_reset, gpio);
#ifdef DEBUG_GPIO
printf("%s: offset " PADDRX "\n", __func__, offset);
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x038,
ppc405_gpio_read, ppc405_gpio_write, gpio);
}
ppc4xx_mmio_register(env, mmio, offset, 0x038,
ppc405_gpio_read, ppc405_gpio_write, gpio);
}
/*****************************************************************************/
@ -1038,19 +1026,17 @@ void ppc405_ocm_init (CPUState *env, unsigned long offset)
ppc405_ocm_t *ocm;
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
if (ocm != NULL) {
ocm->offset = offset;
ocm_reset(ocm);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_ISACNTL,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_DSARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_DSACNTL,
ocm, &dcr_read_ocm, &dcr_write_ocm);
}
ocm->offset = offset;
ocm_reset(ocm);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_ISACNTL,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_DSARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_DSACNTL,
ocm, &dcr_read_ocm, &dcr_write_ocm);
}
/*****************************************************************************/
@ -1286,17 +1272,15 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
ppc4xx_i2c_t *i2c;
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
if (i2c != NULL) {
i2c->base = offset;
i2c->irq = irq;
ppc4xx_i2c_reset(i2c);
i2c->base = offset;
i2c->irq = irq;
ppc4xx_i2c_reset(i2c);
#ifdef DEBUG_I2C
printf("%s: offset " PADDRX "\n", __func__, offset);
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x011,
i2c_read, i2c_write, i2c);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
ppc4xx_mmio_register(env, mmio, offset, 0x011,
i2c_read, i2c_write, i2c);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
/*****************************************************************************/
@ -1568,19 +1552,17 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
int i;
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
if (gpt != NULL) {
gpt->base = offset;
for (i = 0; i < 5; i++)
gpt->irqs[i] = irqs[i];
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
ppc4xx_gpt_reset(gpt);
gpt->base = offset;
for (i = 0; i < 5; i++)
gpt->irqs[i] = irqs[i];
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
ppc4xx_gpt_reset(gpt);
#ifdef DEBUG_GPT
printf("%s: offset " PADDRX "\n", __func__, offset);
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
gpt_read, gpt_write, gpt);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
gpt_read, gpt_write, gpt);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}
/*****************************************************************************/
@ -1802,50 +1784,48 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
int i;
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
if (mal != NULL) {
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
ppc40x_mal_reset(mal);
qemu_register_reset(&ppc40x_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_IER,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP0R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP1R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP2R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP3R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCTP0R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCTP1R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RCBS0,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RCBS1,
mal, &dcr_read_mal, &dcr_write_mal);
}
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
ppc40x_mal_reset(mal);
qemu_register_reset(&ppc40x_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_IER,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP0R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP1R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP2R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP3R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCTP0R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCTP1R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RCBS0,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RCBS1,
mal, &dcr_read_mal, &dcr_write_mal);
}
/*****************************************************************************/
@ -2170,31 +2150,29 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
ppc405cr_cpc_t *cpc;
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
if (cpc != NULL) {
memcpy(cpc->clk_setup, clk_setup,
PPC405CR_CLK_NB * sizeof(clk_setup_t));
cpc->sysclk = sysclk;
cpc->jtagid = 0x42051049;
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc405cr_clk_init(cpc);
qemu_register_reset(ppc405cr_cpc_reset, cpc);
ppc405cr_cpc_reset(cpc);
}
memcpy(cpc->clk_setup, clk_setup,
PPC405CR_CLK_NB * sizeof(clk_setup_t));
cpc->sysclk = sysclk;
cpc->jtagid = 0x42051049;
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc405cr_clk_init(cpc);
qemu_register_reset(ppc405cr_cpc_reset, cpc);
ppc405cr_cpc_reset(cpc);
}
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
@ -2516,38 +2494,36 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
ppc405ep_cpc_t *cpc;
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
if (cpc != NULL) {
memcpy(cpc->clk_setup, clk_setup,
PPC405EP_CLK_NB * sizeof(clk_setup_t));
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
ppc405ep_cpc_reset(cpc);
qemu_register_reset(&ppc405ep_cpc_reset, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
memcpy(cpc->clk_setup, clk_setup,
PPC405EP_CLK_NB * sizeof(clk_setup_t));
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
ppc405ep_cpc_reset(cpc);
qemu_register_reset(&ppc405ep_cpc_reset, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
#if 0
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
#endif
}
}
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],

2
hw/ppc440_bamboo.c
View File

@ -42,8 +42,6 @@ static void *bamboo_load_device_tree(void *addr,
pathlen = snprintf(NULL, 0, "%s/%s", bios_dir, BINARY_DEVICE_TREE_FILE) + 1;
path = qemu_malloc(pathlen);
if (path == NULL)
return NULL;
snprintf(path, pathlen, "%s/%s", bios_dir, BINARY_DEVICE_TREE_FILE);

72
hw/ppc4xx_devs.c
View File

@ -246,18 +246,16 @@ ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
int mmio_memory;
mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
if (mmio != NULL) {
mmio->base = base;
mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
mmio->base = base;
mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
#if defined(DEBUG_MMIO)
printf("%s: base " PADDRX " len %08x %d\n", __func__,
base, TARGET_PAGE_SIZE, mmio_memory);
printf("%s: base " PADDRX " len %08x %d\n", __func__,
base, TARGET_PAGE_SIZE, mmio_memory);
#endif
cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
unassigned_mmio_read, unassigned_mmio_write,
mmio);
}
cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
unassigned_mmio_read, unassigned_mmio_write,
mmio);
return mmio;
}
@ -492,18 +490,16 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
int i;
uic = qemu_mallocz(sizeof(ppcuic_t));
if (uic != NULL) {
uic->dcr_base = dcr_base;
uic->irqs = irqs;
if (has_vr)
uic->use_vectors = 1;
for (i = 0; i < DCR_UICMAX; i++) {
ppc_dcr_register(env, dcr_base + i, uic,
&dcr_read_uic, &dcr_write_uic);
}
qemu_register_reset(ppcuic_reset, uic);
ppcuic_reset(uic);
uic->dcr_base = dcr_base;
uic->irqs = irqs;
if (has_vr)
uic->use_vectors = 1;
for (i = 0; i < DCR_UICMAX; i++) {
ppc_dcr_register(env, dcr_base + i, uic,
&dcr_read_uic, &dcr_write_uic);
}
qemu_register_reset(ppcuic_reset, uic);
ppcuic_reset(uic);
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
@ -829,24 +825,22 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
ppc4xx_sdram_t *sdram;
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
if (sdram != NULL) {
sdram->irq = irq;
sdram->nbanks = nbanks;
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases,
nbanks * sizeof(target_phys_addr_t));
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(target_phys_addr_t));
sdram_reset(sdram);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
if (do_init)
sdram_map_bcr(sdram);
}
sdram->irq = irq;
sdram->nbanks = nbanks;
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases,
nbanks * sizeof(target_phys_addr_t));
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(target_phys_addr_t));
sdram_reset(sdram);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
if (do_init)
sdram_map_bcr(sdram);
}
/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.

2
hw/ppc4xx_pci.c
View File

@ -369,8 +369,6 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
uint8_t *pci_conf;
controller = qemu_mallocz(sizeof(PPC4xxPCIState));
if (!controller)
return NULL;
controller->pci_state.bus = pci_register_bus(ppc4xx_pci_set_irq,
ppc4xx_pci_map_irq,

2
hw/ppc_prep.c
View File

@ -553,8 +553,6 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
BlockDriverState *fd[MAX_FD];
sysctrl = qemu_mallocz(sizeof(sysctrl_t));
if (sysctrl == NULL)
return;
linux_boot = (kernel_filename != NULL);

2
hw/r2d.c
View File

@ -170,8 +170,6 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
r2d_fpga_t *s;
s = qemu_mallocz(sizeof(r2d_fpga_t));
if (!s)
return NULL;
s->irl = irl;

2
hw/rc4030.c
View File

@ -718,8 +718,6 @@ qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
int s_chipset, s_jazzio;
s = qemu_mallocz(sizeof(rc4030State));
if (!s)
return NULL;
*dmas = rc4030_allocate_dmas(s, 4);
*dma_read = rc4030_dma_read;

5
hw/sb16.c
View File

@ -1411,11 +1411,6 @@ int SB16_init (AudioState *audio, qemu_irq *pic)
}
s = qemu_mallocz (sizeof (*s));
if (!s) {
dolog ("Could not allocate memory for SB16 (%zu bytes)\n",
sizeof (*s));
return -1;
}
s->cmd = -1;
s->pic = pic;

2
hw/sbi.c
View File

@ -146,8 +146,6 @@ void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
SBIState *s;
s = qemu_mallocz(sizeof(SBIState));
if (!s)
return NULL;
for (i = 0; i < MAX_CPUS; i++) {
s->cpu_irqs[i] = parent_irq[i];

4
hw/serial.c
View File

@ -732,8 +732,6 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
SerialState *s;
s = qemu_mallocz(sizeof(SerialState));
if (!s)
return NULL;
serial_init_core(s, irq, baudbase, chr);
@ -824,8 +822,6 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
int s_io_memory;
s = qemu_mallocz(sizeof(SerialState));
if (!s)
return NULL;
s->it_shift = it_shift;

4
hw/sh_intc.c
View File

@ -432,9 +432,7 @@ int sh_intc_init(struct intc_desc *desc,
desc->nr_prio_regs = nr_prio_regs;
i = sizeof(struct intc_source) * nr_sources;
desc->sources = malloc(i);
if (!desc->sources)
return -1;
desc->sources = qemu_malloc(i);
memset(desc->sources, 0, i);
for (i = 0; i < desc->nr_sources; i++) {

2
hw/sh_serial.c
View File

@ -376,8 +376,6 @@ void sh_serial_init (target_phys_addr_t base, int feat,
int s_io_memory;
s = qemu_mallocz(sizeof(sh_serial_state));
if (!s)
return;
s->feat = feat;
s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;

4
hw/slavio_intctl.c
View File

@ -381,14 +381,10 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
SLAVIO_CPUINTCTLState *slave;
s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
if (!s)
return NULL;
s->intbit_to_level = intbit_to_level;
for (i = 0; i < MAX_CPUS; i++) {
slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
if (!slave)
return NULL;
slave->cpu = i;
slave->master = s;

2
hw/slavio_misc.c
View File

@ -446,8 +446,6 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
MiscState *s;
s = qemu_mallocz(sizeof(MiscState));
if (!s)
return NULL;
if (base) {
/* 8 bit registers */

2
hw/slavio_timer.c
View File

@ -372,8 +372,6 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
QEMUBH *bh;
s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
if (!s)
return s;
s->irq = irq;
s->master = master;
s->slave_index = slave_index;

2
hw/sparc32_dma.c
View File

@ -248,8 +248,6 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
int dma_io_memory;
s = qemu_mallocz(sizeof(DMAState));
if (!s)
return NULL;
s->irq = parent_irq;
s->iommu = iommu;

2
hw/sun4c_intctl.c
View File

@ -204,8 +204,6 @@ void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
Sun4c_INTCTLState *s;
s = qemu_mallocz(sizeof(Sun4c_INTCTLState));
if (!s)
return NULL;
sun4c_intctl_io_memory = cpu_register_io_memory(0, sun4c_intctl_mem_read,
sun4c_intctl_mem_write, s);

2
hw/tcx.c
View File

@ -499,8 +499,6 @@ void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
int size;
s = qemu_mallocz(sizeof(TCXState));
if (!s)
return;
s->addr = addr;
s->vram_offset = vram_offset;
s->width = width;

2
hw/usb-bt.c
View File

@ -625,8 +625,6 @@ USBDevice *usb_bt_init(HCIInfo *hci)
if (!hci)
return NULL;
s = qemu_mallocz(sizeof(struct USBBtState));
if (!s)
return NULL;
s->dev.opaque = s;
s->dev.speed = USB_SPEED_HIGH;
s->dev.handle_packet = usb_generic_handle_packet;

6
hw/usb-hid.c
View File

@ -851,8 +851,6 @@ USBDevice *usb_tablet_init(void)
USBHIDState *s;
s = qemu_mallocz(sizeof(USBHIDState));
if (!s)
return NULL;
s->dev.speed = USB_SPEED_FULL;
s->dev.handle_packet = usb_generic_handle_packet;
@ -874,8 +872,6 @@ USBDevice *usb_mouse_init(void)
USBHIDState *s;
s = qemu_mallocz(sizeof(USBHIDState));
if (!s)
return NULL;
s->dev.speed = USB_SPEED_FULL;
s->dev.handle_packet = usb_generic_handle_packet;
@ -897,8 +893,6 @@ USBDevice *usb_keyboard_init(void)
USBHIDState *s;
s = qemu_mallocz(sizeof(USBHIDState));
if (!s)
return NULL;
s->dev.speed = USB_SPEED_FULL;
s->dev.handle_packet = usb_generic_handle_packet;

2
hw/usb-hub.c
View File

@ -530,8 +530,6 @@ USBDevice *usb_hub_init(int nb_ports)
if (nb_ports > MAX_PORTS)
return NULL;
s = qemu_mallocz(sizeof(USBHubState));
if (!s)
return NULL;
s->dev.speed = USB_SPEED_FULL;
s->dev.handle_packet = usb_hub_handle_packet;

2
hw/usb-msd.c
View File

@ -548,8 +548,6 @@ USBDevice *usb_msd_init(const char *filename)
}
s = qemu_mallocz(sizeof(MSDState));
if (!s)
return NULL;
bdrv = bdrv_new("usb");
if (bdrv_open2(bdrv, filename, 0, drv) < 0)

2
hw/usb-net.c
View File

@ -1430,8 +1430,6 @@ USBDevice *usb_net_init(NICInfo *nd)
USBNetState *s;
s = qemu_mallocz(sizeof(USBNetState));
if (!s)
return NULL;
s->dev.speed = USB_SPEED_FULL;
s->dev.handle_packet = usb_generic_handle_packet;

2
hw/usb-serial.c
View File

@ -554,8 +554,6 @@ USBDevice *usb_serial_init(const char *filename)
}
filename++;
s = qemu_mallocz(sizeof(USBSerialState));
if (!s)
return NULL;
snprintf(label, sizeof(label), "usbserial%d", index++);
cdrv = qemu_chr_open(label, filename, NULL);

15
hw/usb-uhci.c
View File

@ -155,14 +155,13 @@ typedef struct UHCI_QH {
static UHCIAsync *uhci_async_alloc(UHCIState *s)
{
UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));
if (async) {
memset(&async->packet, 0, sizeof(async->packet));
async->valid = 0;
async->td = 0;
async->token = 0;
async->done = 0;
async->next = NULL;
}
memset(&async->packet, 0, sizeof(async->packet));
async->valid = 0;
async->td = 0;
async->token = 0;
async->done = 0;
async->next = NULL;
return async;
}

2
hw/usb-wacom.c
View File

@ -397,8 +397,6 @@ USBDevice *usb_wacom_init(void)
USBWacomState *s;
s = qemu_mallocz(sizeof(USBWacomState));
if (!s)
return NULL;
s->dev.speed = USB_SPEED_FULL;
s->dev.handle_packet = usb_generic_handle_packet;

2
hw/versatilepb.c
View File

@ -135,8 +135,6 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
int iomemtype;
s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
if (!s)
return NULL;
qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
s->parent = parent;
s->irq = irq;

4
hw/vga.c
View File

@ -2444,8 +2444,6 @@ int isa_vga_init(uint8_t *vga_ram_base,
VGAState *s;
s = qemu_mallocz(sizeof(VGAState));
if (!s)
return -1;
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init(s);
@ -2469,8 +2467,6 @@ int isa_vga_mm_init(uint8_t *vga_ram_base,
VGAState *s;
s = qemu_mallocz(sizeof(VGAState));
if (!s)
return -1;
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_mm_init(s, vram_base, ctrl_base, it_shift);

3
hw/virtio-blk.c
View File

@ -104,8 +104,7 @@ static void virtio_blk_rw_complete(void *opaque, int ret)
static VirtIOBlockReq *virtio_blk_alloc_request(VirtIOBlock *s)
{
VirtIOBlockReq *req = qemu_mallocz(sizeof(*req));
if (req != NULL)
req->dev = s;
req->dev = s;
return req;
}

3
hw/virtio.c
View File

@ -447,8 +447,7 @@ int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem)
sg->iov_len = 2 << 20;
sg->iov_base = qemu_malloc(sg->iov_len);
if (sg->iov_base &&
!(vring_desc_flags(vq, i) & VRING_DESC_F_WRITE)) {
if (!(vring_desc_flags(vq, i) & VRING_DESC_F_WRITE)) {
cpu_physical_memory_read(vring_desc_addr(vq, i),
sg->iov_base,
sg->iov_len);

2
hw/vmmouse.c
View File

@ -275,8 +275,6 @@ void *vmmouse_init(void *m)
DPRINTF("vmmouse_init\n");
s = qemu_mallocz(sizeof(VMMouseState));
if (!s)
return NULL;
s->status = 0xffff;
s->ps2_mouse = m;