mirror of
https://github.com/xemu-project/xemu.git
synced 2024-11-27 05:20:50 +00:00
Delete write only variables
Compiling with GCC 4.6.0 20100925 produced warnings like: /src/qemu/net/tap-win32.c: In function 'tap_win32_open': /src/qemu/net/tap-win32.c:582:12: error: variable 'hThread' set but not used [-Werror=unused-but-set-variable] Fix by removing the unused variables. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
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ae0bfb79aa
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@ -265,13 +265,11 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
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qemu_irq *cpu_exit_irq;
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int via_devfn;
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PCIBus *pci_bus;
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ISADevice *isa_dev;
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uint8_t *eeprom_buf;
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i2c_bus *smbus;
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int i;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DeviceState *eeprom;
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ISADevice *rtc_state;
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CPUState *env;
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/* init CPUs */
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@ -378,9 +376,9 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
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DMA_init(0, cpu_exit_irq);
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/* Super I/O */
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isa_dev = isa_create_simple("i8042");
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isa_create_simple("i8042");
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rtc_state = rtc_init(2000, NULL);
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rtc_init(2000, NULL);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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@ -784,11 +784,7 @@ void mips_malta_init (ram_addr_t ram_size,
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target_long bios_size;
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int64_t kernel_entry;
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PCIBus *pci_bus;
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ISADevice *isa_dev;
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CPUState *env;
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ISADevice *rtc_state;
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FDCtrl *floppy_controller;
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MaltaFPGAState *malta_fpga;
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qemu_irq *i8259;
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qemu_irq *cpu_exit_irq;
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int piix4_devfn;
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@ -851,7 +847,7 @@ void mips_malta_init (ram_addr_t ram_size,
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be = 0;
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#endif
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/* FPGA */
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malta_fpga = malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
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malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
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/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
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if (kernel_filename) {
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@ -957,9 +953,9 @@ void mips_malta_init (ram_addr_t ram_size,
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DMA_init(0, cpu_exit_irq);
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/* Super I/O */
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isa_dev = isa_create_simple("i8042");
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isa_create_simple("i8042");
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rtc_state = rtc_init(2000, NULL);
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rtc_init(2000, NULL);
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serial_isa_init(0, serial_hds[0]);
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serial_isa_init(1, serial_hds[1]);
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if (parallel_hds[0])
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@ -967,7 +963,7 @@ void mips_malta_init (ram_addr_t ram_size,
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for(i = 0; i < MAX_FD; i++) {
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fd[i] = drive_get(IF_FLOPPY, 0, i);
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}
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floppy_controller = fdctrl_init_isa(fd);
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fdctrl_init_isa(fd);
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/* Sound card */
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audio_init(pci_bus);
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@ -167,7 +167,6 @@ void mips_r4k_init (ram_addr_t ram_size,
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int bios_size;
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CPUState *env;
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ResetData *reset_info;
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ISADevice *rtc_state;
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int i;
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qemu_irq *i8259;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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@ -268,7 +267,7 @@ void mips_r4k_init (ram_addr_t ram_size,
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isa_bus_new(NULL);
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isa_bus_irqs(i8259);
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rtc_state = rtc_init(2000, NULL);
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rtc_init(2000, NULL);
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/* Register 64 KB of ISA IO space at 0x14000000 */
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#ifdef TARGET_WORDS_BIGENDIAN
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@ -501,7 +501,6 @@ static void taihu_405ep_init(ram_addr_t ram_size,
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const char *cpu_model)
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{
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char *filename;
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CPUPPCState *env;
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qemu_irq *pic;
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ram_addr_t bios_offset;
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target_phys_addr_t ram_bases[2], ram_sizes[2];
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@ -521,7 +520,7 @@ static void taihu_405ep_init(ram_addr_t ram_size,
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register cpu\n", __func__);
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#endif
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env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
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ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
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kernel_filename == NULL ? 0 : 1);
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/* allocate and load BIOS */
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#ifdef DEBUG_BOARD_INIT
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@ -630,18 +630,11 @@ struct ppc405_dma_t {
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static uint32_t dcr_read_dma (void *opaque, int dcrn)
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{
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ppc405_dma_t *dma;
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dma = opaque;
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return 0;
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}
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static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
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{
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ppc405_dma_t *dma;
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dma = opaque;
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}
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static void ppc405_dma_reset (void *opaque)
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@ -739,9 +732,6 @@ struct ppc405_gpio_t {
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static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
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{
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ppc405_gpio_t *gpio;
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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@ -752,9 +742,6 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
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static void ppc405_gpio_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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ppc405_gpio_t *gpio;
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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@ -763,9 +750,6 @@ static void ppc405_gpio_writeb (void *opaque,
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static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
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{
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ppc405_gpio_t *gpio;
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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@ -776,9 +760,6 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
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static void ppc405_gpio_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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ppc405_gpio_t *gpio;
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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@ -787,9 +768,6 @@ static void ppc405_gpio_writew (void *opaque,
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static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
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{
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ppc405_gpio_t *gpio;
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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@ -800,9 +778,6 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
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static void ppc405_gpio_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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ppc405_gpio_t *gpio;
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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@ -823,9 +798,6 @@ static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
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static void ppc405_gpio_reset (void *opaque)
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{
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ppc405_gpio_t *gpio;
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gpio = opaque;
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}
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static void ppc405_gpio_init(target_phys_addr_t base)
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@ -128,7 +128,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *env = NULL, *envs[MAX_CPUS];
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CPUState *env = NULL;
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char *filename;
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qemu_irq *pic, **openpic_irqs;
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int unin_memory;
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@ -166,7 +166,6 @@ static void ppc_core99_init (ram_addr_t ram_size,
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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envs[i] = env;
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}
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/* allocate RAM */
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@ -66,7 +66,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *env = NULL, *envs[MAX_CPUS];
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CPUState *env = NULL;
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char *filename;
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qemu_irq *pic, **heathrow_irqs;
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int linux_boot, i;
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@ -97,7 +97,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
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/* Set time-base frequency to 16.6 Mhz */
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cpu_ppc_tb_init(env, 16600000UL);
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qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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envs[i] = env;
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}
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/* allocate RAM */
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@ -565,7 +565,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *env = NULL, *envs[MAX_CPUS];
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CPUState *env = NULL;
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char *filename;
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nvram_t nvram;
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M48t59State *m48t59;
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@ -602,7 +602,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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}
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qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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envs[i] = env;
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}
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/* allocate RAM */
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@ -176,7 +176,6 @@ static void mpc8544ds_init(ram_addr_t ram_size,
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int i=0;
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unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
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qemu_irq *irqs, *mpic, *pci_irqs;
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SerialState * serial[2];
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/* Setup CPU */
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env = cpu_ppc_init("e500v2_v30");
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@ -200,13 +199,13 @@ static void mpc8544ds_init(ram_addr_t ram_size,
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/* Serial */
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if (serial_hds[0]) {
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serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
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serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
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0, mpic[12+26], 399193,
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serial_hds[0], 1, 1);
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}
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if (serial_hds[1]) {
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serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
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serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
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0, mpic[12+26], 399193,
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serial_hds[0], 1, 1);
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}
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static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s)
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{
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int i;
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int w_display;
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uint16_t *data_buffer;
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uint8_t *data_display;
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data_buffer = s->vram_ptr;
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w_display = s->scr_width * BITS / 8;
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data_display = ds_get_data(s->ds);
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for(i = 0; i < s->scr_height; i++) {
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#if (BITS == 16)
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@ -85,7 +85,6 @@ static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size,
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uint32_t sysclk)
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{
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CPUState *env;
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qemu_irq *pic;
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qemu_irq *irqs;
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env = cpu_init(cpu_model);
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@ -106,7 +105,7 @@ static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size,
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irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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ppcuic_init(env, irqs, 0x0C0, 0, 1);
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return env;
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}
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@ -236,13 +235,11 @@ static void virtex_init(ram_addr_t ram_size,
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if (kernel_filename) {
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uint64_t entry, low, high;
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uint32_t base32;
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target_phys_addr_t boot_offset;
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/* Boots a kernel elf binary. */
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kernel_size = load_elf(kernel_filename, NULL, NULL,
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&entry, &low, &high, 1, ELF_MACHINE, 0);
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base32 = entry;
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boot_info.bootstrap_pc = entry & 0x00ffffff;
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if (kernel_size < 0) {
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@ -171,7 +171,6 @@ static void wm8750_set_format(WM8750State *s)
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int i;
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struct audsettings in_fmt;
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struct audsettings out_fmt;
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struct audsettings monoout_fmt;
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wm8750_out_flush(s);
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@ -212,10 +211,6 @@ static void wm8750_set_format(WM8750State *s)
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out_fmt.nchannels = 2;
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out_fmt.freq = s->dac_hz;
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out_fmt.fmt = AUD_FMT_S16;
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monoout_fmt.endianness = 0;
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monoout_fmt.nchannels = 1;
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monoout_fmt.freq = s->rate->dac_hz;
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monoout_fmt.fmt = AUD_FMT_S16;
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s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
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CODEC ".speaker", s, wm8750_audio_out_cb, &out_fmt);
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@ -579,7 +579,6 @@ static int tap_win32_open(tap_win32_overlapped_t **phandle,
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} version;
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DWORD version_len;
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DWORD idThread;
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HANDLE hThread;
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if (prefered_name != NULL)
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snprintf(name_buffer, sizeof(name_buffer), "%s", prefered_name);
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@ -623,7 +622,7 @@ static int tap_win32_open(tap_win32_overlapped_t **phandle,
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*phandle = &tap_overlapped;
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hThread = CreateThread(NULL, 0, tap_win32_thread_entry,
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CreateThread(NULL, 0, tap_win32_thread_entry,
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(LPVOID)&tap_overlapped, 0, &idThread);
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return 0;
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}
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4
savevm.c
4
savevm.c
@ -1615,10 +1615,10 @@ static int vmstate_subsection_load(QEMUFile *f, const VMStateDescription *vmsd,
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while (qemu_peek_byte(f) == QEMU_VM_SUBSECTION) {
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char idstr[256];
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int ret;
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uint8_t version_id, subsection, len;
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uint8_t version_id, len;
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const VMStateDescription *sub_vmsd;
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subsection = qemu_get_byte(f);
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qemu_get_byte(f); /* subsection */
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len = qemu_get_byte(f);
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qemu_get_buffer(f, (uint8_t *)idstr, len);
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idstr[len] = 0;
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