mirror of
https://github.com/xemu-project/xemu.git
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i386 hw/: Don't use CPUState
Scripted conversion:
for file in hw/apic.h hw/kvm/apic.c hw/kvmvapic.c hw/pc.c hw/vmport.c hw/xen_machine_pv.c; do
sed -i "s/CPUState/CPUX86State/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber
parent
fc9bb17697
commit
4a8fa5dca1
@ -22,7 +22,7 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
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TPRAccess access);
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/* pc.c */
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int cpu_is_bsp(CPUState *env);
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int cpu_is_bsp(CPUX86State *env);
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DeviceState *cpu_get_current_apic(void);
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#endif
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@ -124,7 +124,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s)
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static void do_inject_external_nmi(void *data)
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{
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APICCommonState *s = data;
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CPUState *env = s->cpu_env;
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CPUX86State *env = s->cpu_env;
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uint32_t lvt;
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int ret;
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@ -142,7 +142,7 @@ static void update_guest_rom_state(VAPICROMState *s)
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write_guest_rom_state(s);
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}
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static int find_real_tpr_addr(VAPICROMState *s, CPUState *env)
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static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
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{
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target_phys_addr_t paddr;
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target_ulong addr;
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@ -185,7 +185,7 @@ static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
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modrm_reg(opcode[1]) == instr->modrm_reg);
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}
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static int evaluate_tpr_instruction(VAPICROMState *s, CPUState *env,
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static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
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target_ulong *pip, TPRAccess access)
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{
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const TPRInstruction *instr;
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@ -267,7 +267,7 @@ instruction_ok:
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return 0;
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}
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static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip)
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static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
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{
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target_phys_addr_t paddr;
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uint32_t rom_state_vaddr;
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@ -330,7 +330,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip)
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* cannot be accessed or is considered invalid. This also ensures that we are
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* not patching the wrong guest.
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*/
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static int get_kpcr_number(CPUState *env)
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static int get_kpcr_number(CPUX86State *env)
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{
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struct kpcr {
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uint8_t fill1[0x1c];
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@ -347,7 +347,7 @@ static int get_kpcr_number(CPUState *env)
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return kpcr.number;
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}
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static int vapic_enable(VAPICROMState *s, CPUState *env)
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static int vapic_enable(VAPICROMState *s, CPUX86State *env)
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{
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int cpu_number = get_kpcr_number(env);
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target_phys_addr_t vapic_paddr;
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@ -367,12 +367,12 @@ static int vapic_enable(VAPICROMState *s, CPUState *env)
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return 0;
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}
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static void patch_byte(CPUState *env, target_ulong addr, uint8_t byte)
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static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte)
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{
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cpu_memory_rw_debug(env, addr, &byte, 1, 1);
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}
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static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip,
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static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
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uint32_t target)
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{
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uint32_t offset;
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@ -382,7 +382,7 @@ static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip,
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cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
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}
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static void patch_instruction(VAPICROMState *s, CPUState *env, target_ulong ip)
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static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip)
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{
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target_phys_addr_t paddr;
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VAPICHandlers *handlers;
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@ -439,7 +439,7 @@ void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
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TPRAccess access)
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{
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VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
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CPUState *env = cpu;
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CPUX86State *env = cpu;
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cpu_synchronize_state(env);
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@ -475,7 +475,7 @@ static void vapic_enable_tpr_reporting(bool enable)
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VAPICEnableTPRReporting info = {
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.enable = enable,
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};
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CPUState *env;
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CPUX86State *env;
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for (env = first_cpu; env != NULL; env = env->next_cpu) {
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info.apic = env->apic_state;
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@ -606,7 +606,7 @@ static int vapic_prepare(VAPICROMState *s)
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static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data,
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unsigned int size)
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{
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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target_phys_addr_t rom_paddr;
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VAPICROMState *s = opaque;
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20
hw/pc.c
20
hw/pc.c
@ -140,7 +140,7 @@ void cpu_smm_register(cpu_set_smm_t callback, void *arg)
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smm_arg = arg;
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}
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void cpu_smm_update(CPUState *env)
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void cpu_smm_update(CPUX86State *env)
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{
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if (smm_set && smm_arg && env == first_cpu)
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smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
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@ -148,7 +148,7 @@ void cpu_smm_update(CPUState *env)
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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int cpu_get_pic_interrupt(CPUX86State *env)
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{
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int intno;
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@ -167,7 +167,7 @@ int cpu_get_pic_interrupt(CPUState *env)
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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CPUState *env = first_cpu;
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CPUX86State *env = first_cpu;
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DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
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if (env->apic_state) {
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@ -522,7 +522,7 @@ type_init(port92_register_types)
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static void handle_a20_line_change(void *opaque, int irq, int level)
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{
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CPUState *cpu = opaque;
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CPUX86State *cpu = opaque;
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/* XXX: send to all CPUs ? */
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/* XXX: add logic to handle multiple A20 line sources */
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@ -869,7 +869,7 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
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nb_ne2k++;
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}
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int cpu_is_bsp(CPUState *env)
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int cpu_is_bsp(CPUX86State *env)
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{
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/* We hard-wire the BSP to the first CPU. */
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return env->cpu_index == 0;
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@ -917,7 +917,7 @@ static DeviceState *apic_init(void *env, uint8_t apic_id)
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void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
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{
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CPUState *s = opaque;
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CPUX86State *s = opaque;
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if (level) {
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cpu_interrupt(s, CPU_INTERRUPT_SMI);
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@ -926,15 +926,15 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
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static void pc_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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CPUX86State *env = opaque;
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cpu_state_reset(env);
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env->halted = !cpu_is_bsp(env);
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}
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static CPUState *pc_new_cpu(const char *cpu_model)
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static CPUX86State *pc_new_cpu(const char *cpu_model)
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{
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CPUState *env;
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CPUX86State *env;
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env = cpu_init(cpu_model);
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if (!env) {
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@ -1070,7 +1070,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
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static void cpu_request_exit(void *opaque, int irq, int level)
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{
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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if (env && level) {
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cpu_exit(env);
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12
hw/vmport.c
12
hw/vmport.c
@ -57,7 +57,7 @@ void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque)
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static uint32_t vmport_ioport_read(void *opaque, uint32_t addr)
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{
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VMPortState *s = opaque;
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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unsigned char command;
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uint32_t eax;
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@ -83,21 +83,21 @@ static uint32_t vmport_ioport_read(void *opaque, uint32_t addr)
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static void vmport_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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env->regs[R_EAX] = vmport_ioport_read(opaque, addr);
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}
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static uint32_t vmport_cmd_get_version(void *opaque, uint32_t addr)
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{
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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env->regs[R_EBX] = VMPORT_MAGIC;
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return 6;
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}
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static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr)
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{
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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env->regs[R_EBX] = 0x1177;
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return ram_size;
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}
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@ -105,7 +105,7 @@ static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr)
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/* vmmouse helpers */
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void vmmouse_get_data(uint32_t *data)
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{
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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data[0] = env->regs[R_EAX]; data[1] = env->regs[R_EBX];
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data[2] = env->regs[R_ECX]; data[3] = env->regs[R_EDX];
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@ -114,7 +114,7 @@ void vmmouse_get_data(uint32_t *data)
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void vmmouse_set_data(const uint32_t *data)
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{
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CPUState *env = cpu_single_env;
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CPUX86State *env = cpu_single_env;
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env->regs[R_EAX] = data[0]; env->regs[R_EBX] = data[1];
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env->regs[R_ECX] = data[2]; env->regs[R_EDX] = data[3];
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@ -36,7 +36,7 @@ static void xen_init_pv(ram_addr_t ram_size,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *env;
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CPUX86State *env;
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DriveInfo *dinfo;
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int i;
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