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target/arm: Allow AArch32 access for PMCCFILTR
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-6-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -994,6 +994,10 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
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PMXEVTYPER_M | PMXEVTYPER_MT | \
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PMXEVTYPER_EVTCOUNT)
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#define PMCCFILTR 0xf8000000
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#define PMCCFILTR_M PMXEVTYPER_M
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#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
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static inline uint32_t pmu_num_counters(CPUARMState *env)
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{
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return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
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@ -1297,10 +1301,26 @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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pmccntr_op_start(env);
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env->cp15.pmccfiltr_el0 = value & 0xfc000000;
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env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0;
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pmccntr_op_finish(env);
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}
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static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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pmccntr_op_start(env);
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/* M is not accessible from AArch32 */
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env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) |
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(value & PMCCFILTR);
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pmccntr_op_finish(env);
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}
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static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/* M is not visible in AArch32 */
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return env->cp15.pmccfiltr_el0 & PMCCFILTR;
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}
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static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -1545,6 +1565,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.readfn = pmccntr_read, .writefn = pmccntr_write,
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.raw_readfn = raw_read, .raw_writefn = raw_write, },
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#endif
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{ .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
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.writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_ALIAS | ARM_CP_IO,
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.resetvalue = 0, },
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{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
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.writefn = pmccfiltr_write, .raw_writefn = raw_write,
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