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target/riscv: Add checks for several RVC reserved operands
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -21,10 +21,16 @@ ld 011 ... ... .. ... 00 @cl_d
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sd 111 ... ... .. ... 00 @cs_d
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# *** RV64C Standard Extension (Quadrant 1) ***
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addiw 001 . ..... ..... 01 @ci
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{
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illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
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addiw 001 . ..... ..... 01 @ci
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}
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subw 100 1 11 ... 00 ... 01 @cs_2
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addw 100 1 11 ... 01 ... 01 @cs_2
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# *** RV64C Standard Extension (Quadrant 2) ***
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ld 011 . ..... ..... 10 @c_ldsp
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{
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illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
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ld 011 . ..... ..... 10 @c_ldsp
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}
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sd 111 . ..... ..... 10 @c_sdsp
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@ -96,6 +96,7 @@ sw 110 ... ... .. ... 00 @cs_w
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addi 000 . ..... ..... 01 @ci
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addi 010 . ..... ..... 01 @c_li
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{
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illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
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addi 011 . 00010 ..... 01 @c_addi16sp
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lui 011 . ..... ..... 01 @c_lui
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}
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@ -113,8 +114,12 @@ bne 111 ... ... ..... 01 @cb_z
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# *** RV32/64C Standard Extension (Quadrant 2) ***
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slli 000 . ..... ..... 10 @c_shift2
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fld 001 . ..... ..... 10 @c_ldsp
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lw 010 . ..... ..... 10 @c_lwsp
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{
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illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
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lw 010 . ..... ..... 10 @c_lwsp
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}
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{
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illegal 100 0 00000 00000 10 # c.jr, RES rs1=0
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jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR
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addi 100 0 ..... ..... 10 @c_mv
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}
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