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target-mips: stop translation after ctc1

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stop translation as ctc1 instruction can change hflags

Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Yongbok Kim 2014-11-01 05:28:38 +00:00 committed by Leon Alrae
parent b7651e9521
commit 4cf8a45f56
1 changed files with 6 additions and 0 deletions
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6
target-mips/translate.c
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@ -7490,12 +7490,15 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
break; break;
case 3: case 3:
/* XXX: For now we support only a single FPU context. */ /* XXX: For now we support only a single FPU context. */
save_cpu_state(ctx, 1);
{ {
TCGv_i32 fs_tmp = tcg_const_i32(rd); TCGv_i32 fs_tmp = tcg_const_i32(rd);
gen_helper_0e2i(ctc1, t0, fs_tmp, rt); gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
tcg_temp_free_i32(fs_tmp); tcg_temp_free_i32(fs_tmp);
} }
/* Stop translation as we may have changed hflags */
ctx->bstate = BS_STOP;
break; break;
/* COP2: Not implemented. */ /* COP2: Not implemented. */
case 4: case 4:
@ -8089,12 +8092,15 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
break; break;
case OPC_CTC1: case OPC_CTC1:
gen_load_gpr(t0, rt); gen_load_gpr(t0, rt);
save_cpu_state(ctx, 1);
{ {
TCGv_i32 fs_tmp = tcg_const_i32(fs); TCGv_i32 fs_tmp = tcg_const_i32(fs);
gen_helper_0e2i(ctc1, t0, fs_tmp, rt); gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
tcg_temp_free_i32(fs_tmp); tcg_temp_free_i32(fs_tmp);
} }
/* Stop translation as we may have changed hflags */
ctx->bstate = BS_STOP;
opn = "ctc1"; opn = "ctc1";
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)