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target-arm: A64: Add SIMD shift by immediate
This implements a subset of the AdvSIMD shift operations (namely all the none saturating or narrowing ones). The actual shift generation code itself is common for both the scalar and vector cases but wrapped with either vector element iteration or the fp reg access. The rounding operations need to take special care to correctly reflect the result of adding rounding bits on high bits as the intermediates do not truncate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée
Peter Maydell
parent
845ea09acc
commit
4d1cef840d
@ -5503,15 +5503,216 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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}
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/*
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* Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
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*
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* This code is handles the common shifting code and is used by both
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* the vector and scalar code.
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*/
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static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
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TCGv_i64 tcg_rnd, bool accumulate,
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bool is_u, int size, int shift)
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{
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bool extended_result = false;
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bool round = !TCGV_IS_UNUSED_I64(tcg_rnd);
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int ext_lshift = 0;
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TCGv_i64 tcg_src_hi;
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if (round && size == 3) {
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extended_result = true;
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ext_lshift = 64 - shift;
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tcg_src_hi = tcg_temp_new_i64();
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} else if (shift == 64) {
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if (!accumulate && is_u) {
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/* result is zero */
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tcg_gen_movi_i64(tcg_res, 0);
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return;
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}
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}
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/* Deal with the rounding step */
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if (round) {
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if (extended_result) {
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TCGv_i64 tcg_zero = tcg_const_i64(0);
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if (!is_u) {
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/* take care of sign extending tcg_res */
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tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
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tcg_gen_add2_i64(tcg_src, tcg_src_hi,
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tcg_src, tcg_src_hi,
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tcg_rnd, tcg_zero);
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} else {
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tcg_gen_add2_i64(tcg_src, tcg_src_hi,
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tcg_src, tcg_zero,
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tcg_rnd, tcg_zero);
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}
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tcg_temp_free_i64(tcg_zero);
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} else {
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tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
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}
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}
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/* Now do the shift right */
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if (round && extended_result) {
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/* extended case, >64 bit precision required */
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if (ext_lshift == 0) {
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/* special case, only high bits matter */
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tcg_gen_mov_i64(tcg_src, tcg_src_hi);
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} else {
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tcg_gen_shri_i64(tcg_src, tcg_src, shift);
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tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift);
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tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi);
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}
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} else {
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if (is_u) {
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if (shift == 64) {
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/* essentially shifting in 64 zeros */
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tcg_gen_movi_i64(tcg_src, 0);
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} else {
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tcg_gen_shri_i64(tcg_src, tcg_src, shift);
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}
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} else {
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if (shift == 64) {
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/* effectively extending the sign-bit */
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tcg_gen_sari_i64(tcg_src, tcg_src, 63);
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} else {
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tcg_gen_sari_i64(tcg_src, tcg_src, shift);
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}
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}
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}
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if (accumulate) {
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tcg_gen_add_i64(tcg_res, tcg_res, tcg_src);
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} else {
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tcg_gen_mov_i64(tcg_res, tcg_src);
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}
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if (extended_result) {
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tcg_temp_free_i64(tcg_src_hi);
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}
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}
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/* Common SHL/SLI - Shift left with an optional insert */
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static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
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bool insert, int shift)
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{
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if (insert) { /* SLI */
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tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift);
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} else { /* SHL */
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tcg_gen_shli_i64(tcg_res, tcg_src, shift);
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}
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}
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/* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
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static void handle_scalar_simd_shri(DisasContext *s,
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bool is_u, int immh, int immb,
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int opcode, int rn, int rd)
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{
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const int size = 3;
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int immhb = immh << 3 | immb;
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int shift = 2 * (8 << size) - immhb;
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bool accumulate = false;
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bool round = false;
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TCGv_i64 tcg_rn;
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TCGv_i64 tcg_rd;
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TCGv_i64 tcg_round;
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if (!extract32(immh, 3, 1)) {
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unallocated_encoding(s);
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return;
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}
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switch (opcode) {
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case 0x02: /* SSRA / USRA (accumulate) */
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accumulate = true;
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break;
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case 0x04: /* SRSHR / URSHR (rounding) */
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round = true;
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break;
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case 0x06: /* SRSRA / URSRA (accum + rounding) */
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accumulate = round = true;
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break;
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}
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if (round) {
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uint64_t round_const = 1ULL << (shift - 1);
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tcg_round = tcg_const_i64(round_const);
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} else {
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TCGV_UNUSED_I64(tcg_round);
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}
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tcg_rn = read_fp_dreg(s, rn);
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tcg_rd = accumulate ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
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handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
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accumulate, is_u, size, shift);
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write_fp_dreg(s, rd, tcg_rd);
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tcg_temp_free_i64(tcg_rn);
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tcg_temp_free_i64(tcg_rd);
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if (round) {
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tcg_temp_free_i64(tcg_round);
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}
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}
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/* SHL/SLI - Scalar shift left */
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static void handle_scalar_simd_shli(DisasContext *s, bool insert,
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int immh, int immb, int opcode,
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int rn, int rd)
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{
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int size = 32 - clz32(immh) - 1;
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int immhb = immh << 3 | immb;
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int shift = immhb - (8 << size);
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TCGv_i64 tcg_rn = new_tmp_a64(s);
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TCGv_i64 tcg_rd = new_tmp_a64(s);
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if (!extract32(immh, 3, 1)) {
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unallocated_encoding(s);
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return;
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}
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tcg_rn = read_fp_dreg(s, rn);
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tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
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handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
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write_fp_dreg(s, rd, tcg_rd);
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tcg_temp_free_i64(tcg_rn);
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tcg_temp_free_i64(tcg_rd);
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}
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/* C3.6.9 AdvSIMD scalar shift by immediate
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* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
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* +-----+---+-------------+------+------+--------+---+------+------+
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* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
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* +-----+---+-------------+------+------+--------+---+------+------+
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*
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* This is the scalar version so it works on a fixed sized registers
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*/
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static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int opcode = extract32(insn, 11, 5);
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int immb = extract32(insn, 16, 3);
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int immh = extract32(insn, 19, 4);
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bool is_u = extract32(insn, 29, 1);
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switch (opcode) {
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case 0x00: /* SSHR / USHR */
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case 0x02: /* SSRA / USRA */
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case 0x04: /* SRSHR / URSHR */
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case 0x06: /* SRSRA / URSRA */
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handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd);
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break;
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case 0x0a: /* SHL / SLI */
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handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
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break;
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default:
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unsupported_encoding(s, insn);
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break;
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}
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}
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/* C3.6.10 AdvSIMD scalar three different
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@ -5816,6 +6017,148 @@ static void disas_simd_scalar_indexed(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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}
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/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
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static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
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int immh, int immb, int opcode, int rn, int rd)
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{
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int size = 32 - clz32(immh) - 1;
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int immhb = immh << 3 | immb;
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int shift = 2 * (8 << size) - immhb;
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bool accumulate = false;
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bool round = false;
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int dsize = is_q ? 128 : 64;
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int esize = 8 << size;
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int elements = dsize/esize;
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TCGMemOp memop = size | (is_u ? 0 : MO_SIGN);
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TCGv_i64 tcg_rn = new_tmp_a64(s);
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TCGv_i64 tcg_rd = new_tmp_a64(s);
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TCGv_i64 tcg_round;
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int i;
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if (extract32(immh, 3, 1) && !is_q) {
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unallocated_encoding(s);
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return;
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}
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if (size > 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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switch (opcode) {
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case 0x02: /* SSRA / USRA (accumulate) */
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accumulate = true;
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break;
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case 0x04: /* SRSHR / URSHR (rounding) */
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round = true;
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break;
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case 0x06: /* SRSRA / URSRA (accum + rounding) */
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accumulate = round = true;
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break;
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}
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if (round) {
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uint64_t round_const = 1ULL << (shift - 1);
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tcg_round = tcg_const_i64(round_const);
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} else {
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TCGV_UNUSED_I64(tcg_round);
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}
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for (i = 0; i < elements; i++) {
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read_vec_element(s, tcg_rn, rn, i, memop);
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if (accumulate) {
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read_vec_element(s, tcg_rd, rd, i, memop);
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}
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handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
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accumulate, is_u, size, shift);
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write_vec_element(s, tcg_rd, rd, i, size);
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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if (round) {
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tcg_temp_free_i64(tcg_round);
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}
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}
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/* SHL/SLI - Vector shift left */
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static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
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int immh, int immb, int opcode, int rn, int rd)
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{
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int size = 32 - clz32(immh) - 1;
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int immhb = immh << 3 | immb;
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int shift = immhb - (8 << size);
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int dsize = is_q ? 128 : 64;
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int esize = 8 << size;
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int elements = dsize/esize;
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TCGv_i64 tcg_rn = new_tmp_a64(s);
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TCGv_i64 tcg_rd = new_tmp_a64(s);
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int i;
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if (extract32(immh, 3, 1) && !is_q) {
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unallocated_encoding(s);
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return;
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}
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if (size > 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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for (i = 0; i < elements; i++) {
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read_vec_element(s, tcg_rn, rn, i, size);
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if (insert) {
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read_vec_element(s, tcg_rd, rd, i, size);
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}
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handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
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write_vec_element(s, tcg_rd, rd, i, size);
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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}
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/* USHLL/SHLL - Vector shift left with widening */
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static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
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int immh, int immb, int opcode, int rn, int rd)
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{
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int size = 32 - clz32(immh) - 1;
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int immhb = immh << 3 | immb;
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int shift = immhb - (8 << size);
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int dsize = 64;
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int esize = 8 << size;
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int elements = dsize/esize;
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TCGv_i64 tcg_rn = new_tmp_a64(s);
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TCGv_i64 tcg_rd = new_tmp_a64(s);
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int i;
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if (size >= 3) {
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unallocated_encoding(s);
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return;
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}
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/* For the LL variants the store is larger than the load,
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* so if rd == rn we would overwrite parts of our input.
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* So load everything right now and use shifts in the main loop.
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*/
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read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);
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for (i = 0; i < elements; i++) {
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tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);
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ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0);
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tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
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write_vec_element(s, tcg_rd, rd, i, size + 1);
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}
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}
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/* C3.6.14 AdvSIMD shift by immediate
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* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
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* +---+---+---+-------------+------+------+--------+---+------+------+
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@ -5824,7 +6167,35 @@ static void disas_simd_scalar_indexed(DisasContext *s, uint32_t insn)
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*/
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static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int opcode = extract32(insn, 11, 5);
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int immb = extract32(insn, 16, 3);
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int immh = extract32(insn, 19, 4);
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bool is_u = extract32(insn, 29, 1);
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bool is_q = extract32(insn, 30, 1);
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switch (opcode) {
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case 0x00: /* SSHR / USHR */
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case 0x02: /* SSRA / USRA (accumulate) */
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case 0x04: /* SRSHR / URSHR (rounding) */
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case 0x06: /* SRSRA / URSRA (accum + rounding) */
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handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd);
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break;
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case 0x0a: /* SHL / SLI */
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handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd);
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break;
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case 0x14: /* SSHLL / USHLL */
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handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd);
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break;
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default:
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/* We don't currently implement any of the Narrow or saturating shifts;
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* nor do we implement the fixed-point conversions in this
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* encoding group (SCVTF, FCVTZS, UCVTF, FCVTZU).
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*/
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unsupported_encoding(s, insn);
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return;
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}
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}
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static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
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