From 4d6b6c0aec20e78c966b857c520fe0d242d64b30 Mon Sep 17 00:00:00 2001
From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sun, 23 Jan 2005 20:45:23 +0000
Subject: [PATCH] more fpu functions - x86_64 fixes

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1234 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-i386/helper.c | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/target-i386/helper.c b/target-i386/helper.c
index d9c446ff61..ea2ef5e027 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1454,7 +1454,11 @@ void load_seg(int seg_reg, int selector)
     selector &= 0xffff;
     if ((selector & 0xfffc) == 0) {
         /* null selector case */
-        if (seg_reg == R_SS)
+        if (seg_reg == R_SS
+#ifdef TARGET_X86_64
+            && !(env->hflags & HF_CS64_MASK)
+#endif
+            )
             raise_exception_err(EXCP0D_GPF, 0);
         cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
     } else {
@@ -2146,6 +2150,7 @@ void helper_sysexit(void)
 
 void helper_movl_crN_T0(int reg)
 {
+#if !defined(CONFIG_USER_ONLY) 
     switch(reg) {
     case 0:
         cpu_x86_update_cr0(env, T0);
@@ -2156,10 +2161,14 @@ void helper_movl_crN_T0(int reg)
     case 4:
         cpu_x86_update_cr4(env, T0);
         break;
+    case 8:
+        cpu_set_apic_tpr(env, T0);
+        break;
     default:
         env->cr[reg] = T0;
         break;
     }
+#endif
 }
 
 /* XXX: do more */
@@ -3227,6 +3236,25 @@ float approx_rcp(float a)
     return 1.0 / a;
 }
 
+/* XXX: find a better solution */
+double helper_sqrt(double a)
+{
+    return sqrt(a);
+}
+
+/* XXX: move that to another file */
+#if defined(__powerpc__)
+/* better to call an helper on ppc */
+float int32_to_float32(int32_t a)
+{
+    return (float)a;
+}
+
+double int32_to_float64(int32_t a)
+{
+    return (double)a;
+}
+#endif
 
 #if !defined(CONFIG_USER_ONLY)