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ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper

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and use this helper to exclude CPUs which are not enabled in the XIVE
controller.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-11-25 07:58:06 +01:00 committed by David Gibson
parent 4a89e20458
commit 5014c60261
2 changed files with 24 additions and 0 deletions
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19
hw/intc/pnv_xive.c
View File

@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
}
/*
* One bit per thread id. The first register PC_THREAD_EN_REG0 covers
* the first cores 0-15 (normal) of the chip or 0-7 (fused). The
* second register covers cores 16-23 (normal) or 8-11 (fused).
*/
static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
{
int pir = ppc_cpu_pir(cpu);
uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
uint32_t bit = pir & 0x3f;
return xive->regs[reg >> 3] & PPC_BIT(bit);
}
static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
XiveTCTX *tctx;
int ring;
if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
continue;
}
tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
/*

5
include/hw/ppc/pnv.h
View File

@ -99,6 +99,11 @@ typedef struct Pnv9Chip {
PnvQuad *quads;
} Pnv9Chip;
/*
* A SMT8 fused core is a pair of SMT4 cores.
*/
#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
typedef struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;