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VFIO updates
- Correction to BAR overflow - Fix error sign - Reset workaround for AMD Bonaire & Hawaii GPUs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVP8LTAAoJECObm247sIsiKiQQAKVLMuxjSSUSDlu5L2tXWUIA EjP3S7Ir8gGgCTNQ97wYGHb/yuIe36z4TP6aTaXB+F6i7PxZIvObnMm35C08BZIg 9WM5ts6duvrPHr2gvhtm9P0WJhtzUbIhGpJ2oI6dLXOHcqdSe6T5OKp23kERJ0Q1 7Il0jk59cs5ts82mkFauQp7jmXBUwjChxDPVXUCqu4SF6MnBVGTXUv7kp/dOv9NW 9BJ+SnHPiVfAqSr+ASZ0jzeR4uOALQiJs8qwiSGSahAxbC2qLoknYl60OTq8zCWL GWIkFUqeVcdX6+0pheWll4apK94Leu8esSs89fjJe9qyBMLCzKoemG8qVMuRkB9H fPjeyePeuTvw190eKYdrvYY6FAAGLGc4TAY0peU+5FZRXJIaEDehmq3/6H7gSQ5l a7CugBh90uwZ99qCtTaWgPQU2rELxZKomA6+V6An7rDh0peSevtLNcpHsMln81RW k70LTSKk0JDfUWiZntjC4oTBzBZfetU2Git5VCwrRKmtGs86xIuZvA0w8a3bDNMR mFPvgw0CZF2hExcxaEFo655YJWpWNCKfR4WJ7chMsPLry4QJwaKmQYUekvsLaxQl RCmG80fjR+l3uJz/MULonYLICx1sknSkCjrKwS7obsOeRS5fHvRApaw3e7EkoIra r3tVXR847/o95vVlEf+n =yNld -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20150428.0' into staging VFIO updates - Correction to BAR overflow - Fix error sign - Reset workaround for AMD Bonaire & Hawaii GPUs # gpg: Signature made Tue Apr 28 18:26:43 2015 BST using RSA key ID 3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" * remotes/awilliam/tags/vfio-update-20150428.0: vfio-pci: Reset workaround for AMD Bonaire and Hawaii GPUs vfio-pci: Fix error path sign vfio-pci: Further fix BAR size overflow Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
52b7aba62f
166
hw/vfio/pci.c
166
hw/vfio/pci.c
@ -154,6 +154,7 @@ typedef struct VFIOPCIDevice {
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PCIHostDeviceAddress host;
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EventNotifier err_notifier;
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EventNotifier req_notifier;
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int (*resetfn)(struct VFIOPCIDevice *);
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uint32_t features;
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#define VFIO_FEATURE_ENABLE_VGA_BIT 0
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#define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
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@ -2400,7 +2401,7 @@ static void vfio_map_bar(VFIOPCIDevice *vdev, int nr)
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if (vdev->msix && vdev->msix->table_bar == nr) {
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uint64_t start;
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start = HOST_PAGE_ALIGN(vdev->msix->table_offset +
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start = HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset +
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(vdev->msix->entries * PCI_MSIX_ENTRY_SIZE));
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size = start < bar->region.size ? bar->region.size - start : 0;
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@ -3325,6 +3326,162 @@ static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev)
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vdev->req_enabled = false;
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}
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/*
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* AMD Radeon PCI config reset, based on Linux:
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* drivers/gpu/drm/radeon/ci_smc.c:ci_is_smc_running()
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* drivers/gpu/drm/radeon/radeon_device.c:radeon_pci_config_reset
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* drivers/gpu/drm/radeon/ci_smc.c:ci_reset_smc()
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* drivers/gpu/drm/radeon/ci_smc.c:ci_stop_smc_clock()
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* IDs: include/drm/drm_pciids.h
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* Registers: http://cgit.freedesktop.org/~agd5f/linux/commit/?id=4e2aa447f6f0
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*
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* Bonaire and Hawaii GPUs do not respond to a bus reset. This is a bug in the
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* hardware that should be fixed on future ASICs. The symptom of this is that
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* once the accerlated driver loads, Windows guests will bsod on subsequent
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* attmpts to load the driver, such as after VM reset or shutdown/restart. To
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* work around this, we do an AMD specific PCI config reset, followed by an SMC
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* reset. The PCI config reset only works if SMC firmware is running, so we
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* have a dependency on the state of the device as to whether this reset will
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* be effective. There are still cases where we won't be able to kick the
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* device into working, but this greatly improves the usability overall. The
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* config reset magic is relatively common on AMD GPUs, but the setup and SMC
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* poking is largely ASIC specific.
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*/
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static bool vfio_radeon_smc_is_running(VFIOPCIDevice *vdev)
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{
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uint32_t clk, pc_c;
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/*
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* Registers 200h and 204h are index and data registers for acessing
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* indirect configuration registers within the device.
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*/
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vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000004, 4);
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clk = vfio_region_read(&vdev->bars[5].region, 0x204, 4);
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vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000370, 4);
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pc_c = vfio_region_read(&vdev->bars[5].region, 0x204, 4);
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return (!(clk & 1) && (0x20100 <= pc_c));
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}
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/*
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* The scope of a config reset is controlled by a mode bit in the misc register
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* and a fuse, exposed as a bit in another register. The fuse is the default
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* (0 = GFX, 1 = whole GPU), the misc bit is a toggle, with the forumula
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* scope = !(misc ^ fuse), where the resulting scope is defined the same as
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* the fuse. A truth table therefore tells us that if misc == fuse, we need
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* to flip the value of the bit in the misc register.
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*/
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static void vfio_radeon_set_gfx_only_reset(VFIOPCIDevice *vdev)
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{
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uint32_t misc, fuse;
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bool a, b;
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vfio_region_write(&vdev->bars[5].region, 0x200, 0xc00c0000, 4);
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fuse = vfio_region_read(&vdev->bars[5].region, 0x204, 4);
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b = fuse & 64;
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vfio_region_write(&vdev->bars[5].region, 0x200, 0xc0000010, 4);
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misc = vfio_region_read(&vdev->bars[5].region, 0x204, 4);
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a = misc & 2;
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if (a == b) {
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vfio_region_write(&vdev->bars[5].region, 0x204, misc ^ 2, 4);
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vfio_region_read(&vdev->bars[5].region, 0x204, 4); /* flush */
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}
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}
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static int vfio_radeon_reset(VFIOPCIDevice *vdev)
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{
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PCIDevice *pdev = &vdev->pdev;
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int i, ret = 0;
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uint32_t data;
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/* Defer to a kernel implemented reset */
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if (vdev->vbasedev.reset_works) {
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return -ENODEV;
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}
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/* Enable only memory BAR access */
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vfio_pci_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MEMORY, 2);
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/* Reset only works if SMC firmware is loaded and running */
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if (!vfio_radeon_smc_is_running(vdev)) {
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ret = -EINVAL;
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goto out;
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}
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/* Make sure only the GFX function is reset */
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vfio_radeon_set_gfx_only_reset(vdev);
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/* AMD PCI config reset */
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vfio_pci_write_config(pdev, 0x7c, 0x39d5e86b, 4);
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usleep(100);
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/* Read back the memory size to make sure we're out of reset */
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for (i = 0; i < 100000; i++) {
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if (vfio_region_read(&vdev->bars[5].region, 0x5428, 4) != 0xffffffff) {
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break;
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}
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usleep(1);
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}
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/* Reset SMC */
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vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000000, 4);
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data = vfio_region_read(&vdev->bars[5].region, 0x204, 4);
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data |= 1;
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vfio_region_write(&vdev->bars[5].region, 0x204, data, 4);
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/* Disable SMC clock */
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vfio_region_write(&vdev->bars[5].region, 0x200, 0x80000004, 4);
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data = vfio_region_read(&vdev->bars[5].region, 0x204, 4);
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data |= 1;
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vfio_region_write(&vdev->bars[5].region, 0x204, data, 4);
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out:
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/* Restore PCI command register */
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vfio_pci_write_config(pdev, PCI_COMMAND, 0, 2);
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return ret;
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}
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static void vfio_setup_resetfn(VFIOPCIDevice *vdev)
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{
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PCIDevice *pdev = &vdev->pdev;
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uint16_t vendor, device;
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vendor = pci_get_word(pdev->config + PCI_VENDOR_ID);
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device = pci_get_word(pdev->config + PCI_DEVICE_ID);
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switch (vendor) {
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case 0x1002:
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switch (device) {
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/* Bonaire */
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case 0x6649: /* Bonaire [FirePro W5100] */
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case 0x6650:
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case 0x6651:
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case 0x6658: /* Bonaire XTX [Radeon R7 260X] */
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case 0x665c: /* Bonaire XT [Radeon HD 7790/8770 / R9 260 OEM] */
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case 0x665d: /* Bonaire [Radeon R7 200 Series] */
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/* Hawaii */
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case 0x67A0: /* Hawaii XT GL [FirePro W9100] */
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case 0x67A1: /* Hawaii PRO GL [FirePro W8100] */
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case 0x67A2:
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case 0x67A8:
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case 0x67A9:
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case 0x67AA:
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case 0x67B0: /* Hawaii XT [Radeon R9 290X] */
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case 0x67B1: /* Hawaii PRO [Radeon R9 290] */
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case 0x67B8:
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case 0x67B9:
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case 0x67BA:
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case 0x67BE:
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vdev->resetfn = vfio_radeon_reset;
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break;
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}
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break;
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}
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}
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static int vfio_initfn(PCIDevice *pdev)
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{
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VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
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@ -3358,7 +3515,7 @@ static int vfio_initfn(PCIDevice *pdev)
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len = readlink(path, iommu_group_path, sizeof(path));
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if (len <= 0 || len >= sizeof(path)) {
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error_report("vfio: error no iommu_group for device");
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return len < 0 ? -errno : ENAMETOOLONG;
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return len < 0 ? -errno : -ENAMETOOLONG;
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}
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iommu_group_path[len] = 0;
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@ -3473,6 +3630,7 @@ static int vfio_initfn(PCIDevice *pdev)
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vfio_register_err_notifier(vdev);
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vfio_register_req_notifier(vdev);
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vfio_setup_resetfn(vdev);
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return 0;
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@ -3520,6 +3678,10 @@ static void vfio_pci_reset(DeviceState *dev)
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vfio_pci_pre_reset(vdev);
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if (vdev->resetfn && !vdev->resetfn(vdev)) {
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goto post_reset;
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}
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if (vdev->vbasedev.reset_works &&
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(vdev->has_flr || !vdev->has_pm_reset) &&
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!ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) {
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