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Sixth RISC-V PR for QEMU 6.2
- Fix build for riscv hosts - Soft code alphabetically -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmGUyR0ACgkQIeENKd+X cFQDpQf8Dr9uRazG/MTraJsQ+KGbgLvOOOU8pgrl1qdqfgOWW9BII85poFfLbfJH 607HGi6wx9dZJVf6LRE+HBsOyxThQBZeLvYbfzl5Qda1SLkzV9y9lL8pVUcTf++7 P2tEPLkkdrgs1XCeuviNmKwjbfeaQXqSfvI16VBEJziVwfKykaUCp5/5jwoAHmVn khjMzB+69/3V6Wzf0TeKmlYMxBmwlTXBQiAgvjQjNjSYQEkX7UfZgLElU+jSsZxp ys/yOENNFzf/yKjt41UgUY8R751nqX90zcWEgeLs9cfVdaQ94DIEMnYh52JIoVrn LuC3x4NWnP8Om9f89BFZnB/IFyRmpw== =a7QR -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu into staging Sixth RISC-V PR for QEMU 6.2 - Fix build for riscv hosts - Soft code alphabetically # gpg: Signature made Wed 17 Nov 2021 10:19:25 AM CET # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu: meson.build: Merge riscv32 and riscv64 cpu family target/riscv: machine: Sort the .subsections Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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commit
52cebbfc13
@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
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'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
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cpu = host_machine.cpu_family()
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# Unify riscv* to a single family.
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if cpu in ['riscv32', 'riscv64']
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cpu = 'riscv'
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endif
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targetos = host_machine.system()
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if cpu in ['x86', 'x86_64']
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@ -76,56 +76,6 @@ static bool hyper_needed(void *opaque)
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return riscv_has_ext(env, RVH);
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}
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static bool vector_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVV);
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}
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static bool pointermasking_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVJ);
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}
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static const VMStateDescription vmstate_vector = {
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.name = "cpu/vector",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = vector_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
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VMSTATE_UINTTL(env.vxrm, RISCVCPU),
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VMSTATE_UINTTL(env.vxsat, RISCVCPU),
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VMSTATE_UINTTL(env.vl, RISCVCPU),
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VMSTATE_UINTTL(env.vstart, RISCVCPU),
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VMSTATE_UINTTL(env.vtype, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pointermasking = {
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.name = "cpu/pointer_masking",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pointermasking_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.mmte, RISCVCPU),
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VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
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VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
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VMSTATE_UINTTL(env.spmmask, RISCVCPU),
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VMSTATE_UINTTL(env.spmbase, RISCVCPU),
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VMSTATE_UINTTL(env.upmmask, RISCVCPU),
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VMSTATE_UINTTL(env.upmbase, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_hyper = {
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.name = "cpu/hyper",
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.version_id = 1,
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@ -164,6 +114,56 @@ static const VMStateDescription vmstate_hyper = {
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}
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};
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static bool vector_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVV);
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}
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static const VMStateDescription vmstate_vector = {
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.name = "cpu/vector",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = vector_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
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VMSTATE_UINTTL(env.vxrm, RISCVCPU),
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VMSTATE_UINTTL(env.vxsat, RISCVCPU),
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VMSTATE_UINTTL(env.vl, RISCVCPU),
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VMSTATE_UINTTL(env.vstart, RISCVCPU),
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VMSTATE_UINTTL(env.vtype, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool pointermasking_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVJ);
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}
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static const VMStateDescription vmstate_pointermasking = {
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.name = "cpu/pointer_masking",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pointermasking_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.mmte, RISCVCPU),
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VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
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VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
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VMSTATE_UINTTL(env.spmmask, RISCVCPU),
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VMSTATE_UINTTL(env.spmbase, RISCVCPU),
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VMSTATE_UINTTL(env.upmmask, RISCVCPU),
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VMSTATE_UINTTL(env.upmbase, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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const VMStateDescription vmstate_riscv_cpu = {
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.name = "cpu",
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.version_id = 3,
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