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xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass
Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency (struct XilinxSPIPS is found there). Also move out a define and remove two double included headers (while touching the code). Finally, add 4 byte address commands to the FlashCMD enum. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20171126231634.9531-6-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -27,8 +27,6 @@
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#include "sysemu/sysemu.h"
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#include "hw/ptimer.h"
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#include "qemu/log.h"
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#include "qemu/fifo8.h"
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#include "hw/ssi/ssi.h"
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#include "qemu/bitops.h"
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#include "hw/ssi/xilinx_spips.h"
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#include "qapi/error.h"
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@ -116,44 +114,11 @@
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/* 16MB per linear region */
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#define LQSPI_ADDRESS_BITS 24
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/* Bite off 4k chunks at a time */
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#define LQSPI_CACHE_SIZE 1024
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#define SNOOP_CHECKING 0xFF
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#define SNOOP_NONE 0xFE
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#define SNOOP_STRIPING 0
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typedef enum {
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READ = 0x3,
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FAST_READ = 0xb,
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DOR = 0x3b,
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QOR = 0x6b,
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DIOR = 0xbb,
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QIOR = 0xeb,
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PP = 0x2,
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DPP = 0xa2,
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QPP = 0x32,
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} FlashCMD;
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typedef struct {
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XilinxSPIPS parent_obj;
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uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
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hwaddr lqspi_cached_addr;
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Error *migration_blocker;
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bool mmio_execution_enabled;
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} XilinxQSPIPS;
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typedef struct XilinxSPIPSClass {
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SysBusDeviceClass parent_class;
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const MemoryRegionOps *reg_ops;
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uint32_t rx_fifo_size;
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uint32_t tx_fifo_size;
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} XilinxSPIPSClass;
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static inline int num_effective_busses(XilinxSPIPS *s)
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{
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return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
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@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS;
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#define XLNX_SPIPS_R_MAX (0x100 / 4)
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/* Bite off 4k chunks at a time */
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#define LQSPI_CACHE_SIZE 1024
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typedef enum {
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READ = 0x3, READ_4 = 0x13,
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FAST_READ = 0xb, FAST_READ_4 = 0x0c,
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DOR = 0x3b, DOR_4 = 0x3c,
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QOR = 0x6b, QOR_4 = 0x6c,
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DIOR = 0xbb, DIOR_4 = 0xbc,
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QIOR = 0xeb, QIOR_4 = 0xec,
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PP = 0x2, PP_4 = 0x12,
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DPP = 0xa2,
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QPP = 0x32, QPP_4 = 0x34,
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} FlashCMD;
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struct XilinxSPIPS {
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SysBusDevice parent_obj;
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@ -56,6 +72,24 @@ struct XilinxSPIPS {
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uint32_t regs[XLNX_SPIPS_R_MAX];
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};
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typedef struct {
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XilinxSPIPS parent_obj;
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uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
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hwaddr lqspi_cached_addr;
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Error *migration_blocker;
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bool mmio_execution_enabled;
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} XilinxQSPIPS;
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typedef struct XilinxSPIPSClass {
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SysBusDeviceClass parent_class;
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const MemoryRegionOps *reg_ops;
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uint32_t rx_fifo_size;
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uint32_t tx_fifo_size;
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} XilinxSPIPSClass;
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#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
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#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
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