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reset refactoring queue:

Browse Source 
* remove uses of qdev_reset_all(), qbus_reset_all(), device_legacy_reset()
  * convert various devices to 3-phase reset, so we can remove their
    uses of device_class_set_parent_reset()
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmOc5fcZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3v9yD/9eSVWT5cEtdZbPyJqe/5z3
 ssxNW31Zu/2rdhEdKHGS5Kf9S1KpUKhjB5ypLjFWsQPUL0pVeZ5Wjf7Dr8Bthsa0
 gbidpPsap+VL/ZzTy2BU0E+BRIIsh1AqLhxbBFAPIfwdeAfZkMdOkRUMXYQJqIEs
 4zqEd2//2H+RRBnVBDMkDN2TgiCxJp0ysYTB8lTEqM+FENSxQBMA8qzlITyn0pPt
 CSsLFKWf9wT/OSlaij7D/r9zfKq6JdeHaqFs3ds/a3vndkwxjiwzqmZCqbA1e8Sx
 2JIYTegyDBe7QsMXA5FxOHGR/Z9ZYhPPEAbHcVgZXwT3VASd7olS+qbCkwyj4bYX
 DeyhjH93NFqv1N+n9GRGV4ox/yIoMU+9b909Dwwi1uNRzWy5/FNQUc2BFY2y3j4s
 hFZNYrB7/WubwXIxPowj9AWugWLGOz/U/62hNigKUhKw+auDUYzYOdTXxMgKOKbz
 R4FrgKrTJcNrrfq+kIxQOMoF/LHZxdBtuGvueDSXlyEd2CXwKwd7B2m5pMybUSwj
 po/gD6G3As4jtUxqxVbdDvO8E7V2hIc4HghXMpgb3Q1plj60iBSOx/dezdrRa7UO
 dWGp+X0wkD7mvUizblwTrPr8xL9wPRIr8GzbIokpckzmm9d7CWVxnpcCNXhYB/Ol
 SGNQ4fcuqRrFq6Ey0Rbe0Q==
 =fBps
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20221216' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

reset refactoring queue:
 * remove uses of qdev_reset_all(), qbus_reset_all(), device_legacy_reset()
 * convert various devices to 3-phase reset, so we can remove their
   uses of device_class_set_parent_reset()

# gpg: Signature made Fri 16 Dec 2022 21:41:11 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20221216' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
  hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset
  hw/intc/xics: Convert TYPE_ICS to 3-phase reset
  hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset()
  pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset
  pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset
  hw/display/virtio-vga: Convert TYPE_VIRTIO_VGA_BASE to 3-phase reset
  hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset
  target/xtensa: Convert to 3-phase reset
  target/tricore: Convert to 3-phase reset
  target/sparc: Convert to 3-phase reset
  target/sh4: Convert to 3-phase reset
  target/rx: Convert to 3-phase reset
  target/riscv: Convert to 3-phase reset
  target/ppc: Convert to 3-phase reset
  target/openrisc: Convert to 3-phase reset
  target/nios2: Convert to 3-phase reset
  target/mips: Convert to 3-phase reset
  target/microblaze: Convert to 3-phase reset
  target/m68k: Convert to 3-phase reset
  target/loongarch: Convert to 3-phase reset
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-12-17 14:12:52 +00:00
commit 55745005e9
66 changed files with 321 additions and 314 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/core/cpu-common.c
View File

@ -116,9 +116,9 @@ void cpu_reset(CPUState *cpu)
trace_guest_cpu_reset(cpu);
}
static void cpu_common_reset(DeviceState *dev)
static void cpu_common_reset_hold(Object *obj)
{
CPUState *cpu = CPU(dev);
CPUState *cpu = CPU(obj);
CPUClass *cc = CPU_GET_CLASS(cpu);
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
@ -259,6 +259,7 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
static void cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
CPUClass *k = CPU_CLASS(klass);
k->parse_features = cpu_common_parse_features;
@ -269,7 +270,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
dc->reset = cpu_common_reset;
rc->phases.hold = cpu_common_reset_hold;
cpu_class_init_props(dc);
/*
* Reason: CPUs still need special care by board code: wiring up

64
hw/core/qdev.c
View File

@ -250,60 +250,6 @@ void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
dev->alias_required_for_version = required_for_version;
}
static int qdev_prereset(DeviceState *dev, void *opaque)
{
trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev)));
return 0;
}
static int qbus_prereset(BusState *bus, void *opaque)
{
trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus)));
return 0;
}
static int qdev_reset_one(DeviceState *dev, void *opaque)
{
device_legacy_reset(dev);
return 0;
}
static int qbus_reset_one(BusState *bus, void *opaque)
{
BusClass *bc = BUS_GET_CLASS(bus);
trace_qbus_reset(bus, object_get_typename(OBJECT(bus)));
if (bc->reset) {
bc->reset(bus);
}
return 0;
}
void qdev_reset_all(DeviceState *dev)
{
trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev)));
qdev_walk_children(dev, qdev_prereset, qbus_prereset,
qdev_reset_one, qbus_reset_one, NULL);
}
void qdev_reset_all_fn(void *opaque)
{
qdev_reset_all(DEVICE(opaque));
}
void qbus_reset_all(BusState *bus)
{
trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus)));
qbus_walk_children(bus, qdev_prereset, qbus_prereset,
qdev_reset_one, qbus_reset_one, NULL);
}
void qbus_reset_all_fn(void *opaque)
{
BusState *bus = opaque;
qbus_reset_all(bus);
}
void device_cold_reset(DeviceState *dev)
{
resettable_reset(OBJECT(dev), RESET_TYPE_COLD);
@ -922,16 +868,6 @@ void device_class_set_parent_unrealize(DeviceClass *dc,
dc->unrealize = dev_unrealize;
}
void device_legacy_reset(DeviceState *dev)
{
DeviceClass *klass = DEVICE_GET_CLASS(dev);
trace_qdev_reset(dev, object_get_typename(OBJECT(dev)));
if (klass->reset) {
klass->reset(dev);
}
}
Object *qdev_get_machine(void)
{
static Object *dev;

6
hw/core/trace-events
View File

@ -2,12 +2,6 @@
loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d"
# qdev.c
qdev_reset(void *obj, const char *objtype) "obj=%p(%s)"
qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)"
# resettable.c

15
hw/display/virtio-vga.c
View File

@ -165,13 +165,15 @@ static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
}
}
static void virtio_vga_base_reset(DeviceState *dev)
static void virtio_vga_base_reset_hold(Object *obj)
{
VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(dev);
VirtIOVGABase *vvga = VIRTIO_VGA_BASE(dev);
VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj);
VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj);
/* reset virtio-gpu */
klass->parent_reset(dev);
if (klass->parent_phases.hold) {
klass->parent_phases.hold(obj);
}
/* reset vga */
vga_common_reset(&vvga->vga);
@ -203,13 +205,14 @@ static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass);
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
device_class_set_props(dc, virtio_vga_base_properties);
dc->vmsd = &vmstate_virtio_vga_base;
dc->hotpluggable = false;
device_class_set_parent_reset(dc, virtio_vga_base_reset,
&v->parent_reset);
resettable_class_set_parent_phases(rc, NULL, virtio_vga_base_reset_hold,
NULL, &v->parent_phases);
k->realize = virtio_vga_base_realize;
pcidev_k->romfile = "vgabios-virtio.bin";

2
hw/display/virtio-vga.h
View File

@ -23,7 +23,7 @@ struct VirtIOVGABase {
struct VirtIOVGABaseClass {
VirtioPCIClass parent_class;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
#endif /* VIRTIO_VGA_H */

4
hw/hyperv/vmbus.c
View File

@ -1578,7 +1578,7 @@ static bool vmbus_initialized(VMBus *vmbus)
static void vmbus_reset_all(VMBus *vmbus)
{
qbus_reset_all(BUS(vmbus));
bus_cold_reset(BUS(vmbus));
}
static void post_msg(VMBus *vmbus, void *msgdata, uint32_t msglen)
@ -2035,7 +2035,7 @@ static void vdev_reset_on_close(VMBusDevice *vdev)
}
/* all channels closed -- reset device */
qdev_reset_all(DEVICE(vdev));
device_cold_reset(DEVICE(vdev));
}
static void handle_close_channel(VMBus *vmbus, vmbus_message_close_channel *msg,

2
hw/i386/xen/xen_platform.c
View File

@ -177,7 +177,7 @@ static void pci_xen_ide_unplug(DeviceState *dev, bool aux)
blk_unref(blk);
}
}
qdev_reset_all(dev);
device_cold_reset(dev);
}
static void unplug_disks(PCIBus *b, PCIDevice *d, void *opaque)

2
hw/input/adb.c
View File

@ -43,7 +43,7 @@ static const char *adb_commands[] = {
static void adb_device_reset(ADBDevice *d)
{
qdev_reset_all(DEVICE(d));
device_cold_reset(DEVICE(d));
}
static int do_adb_request(ADBBusState *s, uint8_t *obuf, const uint8_t *buf,

45
hw/input/ps2.c
View File

@ -1001,12 +1001,18 @@ void ps2_write_mouse(PS2MouseState *s, int val)
}
}
static void ps2_reset(DeviceState *dev)
static void ps2_reset_hold(Object *obj)
{
PS2State *s = PS2_DEVICE(dev);
PS2State *s = PS2_DEVICE(obj);
s->write_cmd = -1;
ps2_reset_queue(s);
}
static void ps2_reset_exit(Object *obj)
{
PS2State *s = PS2_DEVICE(obj);
ps2_lower_irq(s);
}
@ -1036,13 +1042,16 @@ static void ps2_common_post_load(PS2State *s)
q->cwptr = ccount ? (q->rptr + ccount) & (PS2_BUFFER_SIZE - 1) : -1;
}
static void ps2_kbd_reset(DeviceState *dev)
static void ps2_kbd_reset_hold(Object *obj)
{
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(dev);
PS2KbdState *s = PS2_KBD_DEVICE(dev);
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
PS2KbdState *s = PS2_KBD_DEVICE(obj);
trace_ps2_kbd_reset(s);
ps2dc->parent_reset(dev);
if (ps2dc->parent_phases.hold) {
ps2dc->parent_phases.hold(obj);
}
s->scan_enabled = 1;
s->translate = 0;
@ -1050,13 +1059,16 @@ static void ps2_kbd_reset(DeviceState *dev)
s->modifiers = 0;
}
static void ps2_mouse_reset(DeviceState *dev)
static void ps2_mouse_reset_hold(Object *obj)
{
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(dev);
PS2MouseState *s = PS2_MOUSE_DEVICE(dev);
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
PS2MouseState *s = PS2_MOUSE_DEVICE(obj);
trace_ps2_mouse_reset(s);
ps2dc->parent_reset(dev);
if (ps2dc->parent_phases.hold) {
ps2dc->parent_phases.hold(obj);
}
s->mouse_status = 0;
s->mouse_resolution = 0;
@ -1239,10 +1251,12 @@ static void ps2_mouse_realize(DeviceState *dev, Error **errp)
static void ps2_kbd_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
dc->realize = ps2_kbd_realize;
device_class_set_parent_reset(dc, ps2_kbd_reset, &ps2dc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, ps2_kbd_reset_hold, NULL,
&ps2dc->parent_phases);
dc->vmsd = &vmstate_ps2_keyboard;
}
@ -1256,11 +1270,12 @@ static const TypeInfo ps2_kbd_info = {
static void ps2_mouse_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
dc->realize = ps2_mouse_realize;
device_class_set_parent_reset(dc, ps2_mouse_reset,
&ps2dc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, ps2_mouse_reset_hold, NULL,
&ps2dc->parent_phases);
dc->vmsd = &vmstate_ps2_mouse;
}
@ -1281,8 +1296,10 @@ static void ps2_init(Object *obj)
static void ps2_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->reset = ps2_reset;
rc->phases.hold = ps2_reset_hold;
rc->phases.exit = ps2_reset_exit;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

11
hw/intc/xics.c
View File

@ -564,9 +564,9 @@ static void ics_reset_irq(ICSIRQState *irq)
irq->saved_priority = 0xff;
}
static void ics_reset(DeviceState *dev)
static void ics_reset_hold(Object *obj)
{
ICSState *ics = ICS(dev);
ICSState *ics = ICS(obj);
g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
int i;
@ -584,7 +584,7 @@ static void ics_reset(DeviceState *dev)
if (kvm_irqchip_in_kernel()) {
Error *local_err = NULL;
ics_set_kvm_state(ICS(dev), &local_err);
ics_set_kvm_state(ics, &local_err);
if (local_err) {
error_report_err(local_err);
}
@ -593,7 +593,7 @@ static void ics_reset(DeviceState *dev)
static void ics_reset_handler(void *dev)
{
ics_reset(dev);
device_cold_reset(dev);
}
static void ics_realize(DeviceState *dev, Error **errp)
@ -688,16 +688,17 @@ static Property ics_properties[] = {
static void ics_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = ics_realize;
device_class_set_props(dc, ics_properties);
dc->reset = ics_reset;
dc->vmsd = &vmstate_ics;
/*
* Reason: part of XICS interrupt controller, needs to be wired up,
* e.g. by spapr_irq_init().
*/
dc->user_creatable = false;
rc->phases.hold = ics_reset_hold;
}
static const TypeInfo ics_info = {

26
hw/misc/mac_via.c
View File

@ -975,14 +975,16 @@ static int via1_post_load(void *opaque, int version_id)
}
/* VIA 1 */
static void mos6522_q800_via1_reset(DeviceState *dev)
static void mos6522_q800_via1_reset_hold(Object *obj)
{
MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev);
MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj);
MOS6522State *ms = MOS6522(v1s);
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
ADBBusState *adb_bus = &v1s->adb_bus;
mdc->parent_reset(dev);
if (mdc->parent_phases.hold) {
mdc->parent_phases.hold(obj);
}
ms->timers[0].frequency = VIA_TIMER_FREQ;
ms->timers[1].frequency = VIA_TIMER_FREQ;
@ -1097,11 +1099,12 @@ static Property mos6522_q800_via1_properties[] = {
static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
dc->realize = mos6522_q800_via1_realize;
device_class_set_parent_reset(dc, mos6522_q800_via1_reset,
&mdc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via1_reset_hold,
NULL, &mdc->parent_phases);
dc->vmsd = &vmstate_q800_via1;
device_class_set_props(dc, mos6522_q800_via1_properties);
}
@ -1123,12 +1126,14 @@ static void mos6522_q800_via2_portB_write(MOS6522State *s)
}
}
static void mos6522_q800_via2_reset(DeviceState *dev)
static void mos6522_q800_via2_reset_hold(Object *obj)
{
MOS6522State *ms = MOS6522(dev);
MOS6522State *ms = MOS6522(obj);
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
mdc->parent_reset(dev);
if (mdc->parent_phases.hold) {
mdc->parent_phases.hold(obj);
}
ms->timers[0].frequency = VIA_TIMER_FREQ;
ms->timers[1].frequency = VIA_TIMER_FREQ;
@ -1183,10 +1188,11 @@ static const VMStateDescription vmstate_q800_via2 = {
static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
device_class_set_parent_reset(dc, mos6522_q800_via2_reset,
&mdc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via2_reset_hold,
NULL, &mdc->parent_phases);
dc->vmsd = &vmstate_q800_via2;
mdc->portB_write = mos6522_q800_via2_portB_write;
}

14
hw/misc/macio/cuda.c
View File

@ -589,12 +589,14 @@ static void mos6522_cuda_portB_write(MOS6522State *s)
cuda_update(cs);
}
static void mos6522_cuda_reset(DeviceState *dev)
static void mos6522_cuda_reset_hold(Object *obj)
{
MOS6522State *ms = MOS6522(dev);
MOS6522State *ms = MOS6522(obj);
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
mdc->parent_reset(dev);
if (mdc->parent_phases.hold) {
mdc->parent_phases.hold(obj);
}
ms->timers[0].frequency = CUDA_TIMER_FREQ;
ms->timers[1].frequency = (SCALE_US * 6000) / 4700;
@ -602,11 +604,11 @@ static void mos6522_cuda_reset(DeviceState *dev)
static void mos6522_cuda_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
device_class_set_parent_reset(dc, mos6522_cuda_reset,
&mdc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, mos6522_cuda_reset_hold,
NULL, &mdc->parent_phases);
mdc->portB_write = mos6522_cuda_portB_write;
mdc->get_timer1_counter_value = cuda_get_counter_value;
mdc->get_timer2_counter_value = cuda_get_counter_value;

14
hw/misc/macio/pmu.c
View File

@ -797,14 +797,16 @@ static void mos6522_pmu_portB_write(MOS6522State *s)
pmu_update(ps);
}
static void mos6522_pmu_reset(DeviceState *dev)
static void mos6522_pmu_reset_hold(Object *obj)
{
MOS6522State *ms = MOS6522(dev);
MOS6522State *ms = MOS6522(obj);
MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj);
PMUState *s = container_of(mps, PMUState, mos6522_pmu);
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
mdc->parent_reset(dev);
if (mdc->parent_phases.hold) {
mdc->parent_phases.hold(obj);
}
ms->timers[0].frequency = VIA_TIMER_FREQ;
ms->timers[1].frequency = (SCALE_US * 6000) / 4700;
@ -814,11 +816,11 @@ static void mos6522_pmu_reset(DeviceState *dev)
static void mos6522_pmu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
device_class_set_parent_reset(dc, mos6522_pmu_reset,
&mdc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, mos6522_pmu_reset_hold,
NULL, &mdc->parent_phases);
mdc->portB_write = mos6522_pmu_portB_write;
}

7
hw/misc/mos6522.c
View File

@ -643,9 +643,9 @@ const VMStateDescription vmstate_mos6522 = {
}
};
static void mos6522_reset(DeviceState *dev)
static void mos6522_reset_hold(Object *obj)
{
MOS6522State *s = MOS6522(dev);
MOS6522State *s = MOS6522(obj);
s->b = 0;
s->a = 0;
@ -705,9 +705,10 @@ static Property mos6522_properties[] = {
static void mos6522_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
dc->reset = mos6522_reset;
rc->phases.hold = mos6522_reset_hold;
dc->vmsd = &vmstate_mos6522;
device_class_set_props(dc, mos6522_properties);
mdc->portB_write = mos6522_portB_write;

14
hw/pci-bridge/cxl_root_port.c
View File

@ -138,12 +138,14 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp)
component_bar);
}
static void cxl_rp_reset(DeviceState *dev)
static void cxl_rp_reset_hold(Object *obj)
{
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
CXLRootPort *crp = CXL_ROOT_PORT(dev);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
CXLRootPort *crp = CXL_ROOT_PORT(obj);
rpc->parent_reset(dev);
if (rpc->parent_phases.hold) {
rpc->parent_phases.hold(obj);
}
latch_registers(crp);
}
@ -199,6 +201,7 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc);
k->vendor_id = PCI_VENDOR_ID_INTEL;
@ -209,7 +212,8 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data)
k->config_write = cxl_rp_write_config;
device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize);
device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL,
&rpc->parent_phases);
rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;

8
hw/pci-bridge/pcie_root_port.c
View File

@ -43,9 +43,10 @@ static void rp_write_config(PCIDevice *d, uint32_t address,
pcie_aer_root_write_config(d, address, val, len, root_cmd);
}
static void rp_reset(DeviceState *qdev)
static void rp_reset_hold(Object *obj)
{
PCIDevice *d = PCI_DEVICE(qdev);
PCIDevice *d = PCI_DEVICE(obj);
DeviceState *qdev = DEVICE(obj);
rp_aer_vector_update(d);
pcie_cap_root_reset(d);
@ -171,13 +172,14 @@ static void rp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
k->is_bridge = true;
k->config_write = rp_write_config;
k->realize = rp_realize;
k->exit = rp_exit;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->reset = rp_reset;
rc->phases.hold = rp_reset_hold;
device_class_set_props(dc, rp_props);
}

18
hw/pci-host/pnv_phb.c
View File

@ -199,14 +199,16 @@ static void pnv_phb_class_init(ObjectClass *klass, void *data)
dc->user_creatable = true;
}
static void pnv_phb_root_port_reset(DeviceState *dev)
static void pnv_phb_root_port_reset_hold(Object *obj)
{
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
PCIDevice *d = PCI_DEVICE(dev);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
PCIDevice *d = PCI_DEVICE(obj);
uint8_t *conf = d->config;
rpc->parent_reset(dev);
if (rpc->parent_phases.hold) {
rpc->parent_phases.hold(obj);
}
if (phb_rp->version == 3) {
return;
@ -300,6 +302,7 @@ static Property pnv_phb_root_port_properties[] = {
static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
@ -308,9 +311,8 @@ static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, pnv_phb_root_port_properties);
device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
&rpc->parent_realize);
device_class_set_parent_reset(dc, pnv_phb_root_port_reset,
&rpc->parent_reset);
dc->reset = &pnv_phb_root_port_reset;
resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold,
NULL, &rpc->parent_phases);
dc->user_creatable = true;
k->vendor_id = PCI_VENDOR_ID_IBM;

22
hw/pci-host/pnv_phb3_msi.c
View File

@ -228,22 +228,19 @@ static void phb3_msi_resend(ICSState *ics)
}
}
static void phb3_msi_reset(DeviceState *dev)
static void phb3_msi_reset_hold(Object *obj)
{
Phb3MsiState *msi = PHB3_MSI(dev);
ICSStateClass *icsc = ICS_GET_CLASS(dev);
Phb3MsiState *msi = PHB3_MSI(obj);
ICSStateClass *icsc = ICS_GET_CLASS(obj);
icsc->parent_reset(dev);
if (icsc->parent_phases.hold) {
icsc->parent_phases.hold(obj);
}
memset(msi->rba, 0, sizeof(msi->rba));
msi->rba_sum = 0;
}
static void phb3_msi_reset_handler(void *dev)
{
phb3_msi_reset(dev);
}
void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base,
uint32_t count)
{
@ -272,8 +269,6 @@ static void phb3_msi_realize(DeviceState *dev, Error **errp)
}
msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs);
qemu_register_reset(phb3_msi_reset_handler, dev);
}
static void phb3_msi_instance_init(Object *obj)
@ -294,11 +289,12 @@ static void phb3_msi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ICSStateClass *isc = ICS_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
device_class_set_parent_realize(dc, phb3_msi_realize,
&isc->parent_realize);
device_class_set_parent_reset(dc, phb3_msi_reset,
&isc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, phb3_msi_reset_hold, NULL,
&isc->parent_phases);
isc->reject = phb3_msi_reject;
isc->resend = phb3_msi_resend;

6
hw/pci/pci.c
View File

@ -378,14 +378,14 @@ static void pci_do_device_reset(PCIDevice *dev)
*/
void pci_device_reset(PCIDevice *dev)
{
qdev_reset_all(&dev->qdev);
device_cold_reset(&dev->qdev);
pci_do_device_reset(dev);
}
/*
* Trigger pci bus reset under a given bus.
* Called via qbus_reset_all on RST# assert, after the devices
* have been reset qdev_reset_all-ed already.
* Called via bus_cold_reset on RST# assert, after the devices
* have been reset device_cold_reset-ed already.
*/
static void pcibus_reset(BusState *qbus)
{

2
hw/pci/pci_bridge.c
View File

@ -275,7 +275,7 @@ void pci_bridge_write_config(PCIDevice *d,
newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
/* Trigger hot reset on 0->1 transition. */
qbus_reset_all(BUS(&s->sec_bus));
bus_cold_reset(BUS(&s->sec_bus));
}
}

2
hw/remote/vfio-user-obj.c
View File

@ -678,7 +678,7 @@ static int vfu_object_device_reset(vfu_ctx_t *vfu_ctx, vfu_reset_type_t type)
return 0;
}
qdev_reset_all(DEVICE(o->pci_dev));
device_cold_reset(DEVICE(o->pci_dev));
return 0;
}

2
hw/s390x/s390-pci-inst.c
View File

@ -272,7 +272,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
goto out;
}
device_legacy_reset(DEVICE(pbdev));
device_cold_reset(DEVICE(pbdev));
pbdev->fh &= ~FH_MASK_ENABLE;
pbdev->state = ZPCI_FS_DISABLED;
stl_p(&ressetpci->fh, pbdev->fh);

2
hw/s390x/s390-virtio-ccw.c
View File

@ -118,7 +118,7 @@ static void subsystem_reset(void)
for (i = 0; i < ARRAY_SIZE(reset_dev_types); i++) {
dev = DEVICE(object_resolve_path_type("", reset_dev_types[i], NULL));
if (dev) {
qdev_reset_all(dev);
device_cold_reset(dev);
}
}
}

2
hw/usb/dev-uas.c
View File

@ -791,7 +791,7 @@ static void usb_uas_task(UASDevice *uas, uas_iu *iu)
case UAS_TMF_LOGICAL_UNIT_RESET:
trace_usb_uas_tmf_logical_unit_reset(uas->dev.addr, tag, lun);
qdev_reset_all(&dev->qdev);
device_cold_reset(&dev->qdev);
usb_uas_queue_response(uas, tag, UAS_RC_TMF_COMPLETE);
break;

8
hw/virtio/virtio-pci.c
View File

@ -2008,9 +2008,10 @@ static void virtio_pci_reset(DeviceState *qdev)
}
}
static void virtio_pci_bus_reset(DeviceState *qdev)
static void virtio_pci_bus_reset_hold(Object *obj)
{
PCIDevice *dev = PCI_DEVICE(qdev);
PCIDevice *dev = PCI_DEVICE(obj);
DeviceState *qdev = DEVICE(obj);
virtio_pci_reset(qdev);
@ -2071,6 +2072,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
device_class_set_props(dc, virtio_pci_properties);
k->realize = virtio_pci_realize;
@ -2080,7 +2082,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_OTHERS;
device_class_set_parent_realize(dc, virtio_pci_dc_realize,
&vpciklass->parent_dc_realize);
dc->reset = virtio_pci_bus_reset;
rc->phases.hold = virtio_pci_bus_reset_hold;
}
static const TypeInfo virtio_pci_info = {

2
include/hw/input/ps2.h
View File

@ -36,7 +36,7 @@
struct PS2DeviceClass {
SysBusDeviceClass parent_class;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
/*

2
include/hw/misc/mos6522.h
View File

@ -157,7 +157,7 @@ OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, MOS6522)
struct MOS6522DeviceClass {
DeviceClass parent_class;
DeviceReset parent_reset;
ResettablePhases parent_phases;
void (*portB_write)(MOS6522State *dev);
void (*portA_write)(MOS6522State *dev);
/* These are used to influence the CUDA MacOS timebase calibration */

2
include/hw/pci/pcie_port.h
View File

@ -80,7 +80,7 @@ DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT,
struct PCIERootPortClass {
PCIDeviceClass parent_class;
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
uint8_t (*aer_vector)(const PCIDevice *dev);
int (*interrupts_init)(PCIDevice *dev, Error **errp);

2
include/hw/ppc/xics.h
View File

@ -95,7 +95,7 @@ struct ICSStateClass {
DeviceClass parent_class;
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
void (*reject)(ICSState *s, uint32_t irq);
void (*resend)(ICSState *s);

35
include/hw/qdev-core.h
View File

@ -743,32 +743,6 @@ int qdev_walk_children(DeviceState *dev,
qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
void *opaque);
/**
* @qdev_reset_all:
* Reset @dev. See @qbus_reset_all() for more details.
*
* Note: This function is deprecated and will be removed when it becomes unused.
* Please use device_cold_reset() now.
*/
void qdev_reset_all(DeviceState *dev);
void qdev_reset_all_fn(void *opaque);
/**
* @qbus_reset_all:
* @bus: Bus to be reset.
*
* Reset @bus and perform a bus-level ("hard") reset of all devices connected
* to it, including recursive processing of all buses below @bus itself. A
* hard reset means that qbus_reset_all will reset all state of the device.
* For PCI devices, for example, this will include the base address registers
* or configuration space.
*
* Note: This function is deprecated and will be removed when it becomes unused.
* Please use bus_cold_reset() now.
*/
void qbus_reset_all(BusState *bus);
void qbus_reset_all_fn(void *opaque);
/**
* device_cold_reset:
* Reset device @dev and perform a recursive processing using the resettable
@ -802,15 +776,6 @@ BusState *sysbus_get_default(void);
char *qdev_get_fw_dev_path(DeviceState *dev);
char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev);
/**
* device_legacy_reset:
*
* Reset a single device (by calling the reset method).
* Note: This function is deprecated and will be removed when it becomes unused.
* Please use device_cold_reset() now.
*/
void device_legacy_reset(DeviceState *dev);
void device_class_set_props(DeviceClass *dc, Property *props);
/**

4
target/arm/cpu-qom.h
View File

@ -43,7 +43,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An ARM CPU model.
*/
@ -54,7 +54,7 @@ struct ARMCPUClass {
const ARMCPUInfo *info;
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};

13
target/arm/cpu.c
View File

@ -202,14 +202,16 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
assert(oldvalue == newvalue);
}
static void arm_cpu_reset(DeviceState *dev)
static void arm_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
ARMCPU *cpu = ARM_CPU(s);
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
CPUARMState *env = &cpu->env;
acc->parent_reset(dev);
if (acc->parent_phases.hold) {
acc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUARMState, end_reset_fields));
@ -2211,12 +2213,15 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(acc);
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, arm_cpu_realizefn,
&acc->parent_realize);
device_class_set_props(dc, arm_cpu_properties);
device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
&acc->parent_phases);
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;

4
target/avr/cpu-qom.h
View File

@ -31,7 +31,7 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
/**
* AVRCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A AVR CPU model.
*/
@ -40,7 +40,7 @@ struct AVRCPUClass {
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};

13
target/avr/cpu.c
View File

@ -67,14 +67,16 @@ static void avr_restore_state_to_opc(CPUState *cs,
env->pc_w = data[0];
}
static void avr_cpu_reset(DeviceState *ds)
static void avr_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(ds);
CPUState *cs = CPU(obj);
AVRCPU *cpu = AVR_CPU(cs);
AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
CPUAVRState *env = &cpu->env;
mcc->parent_reset(ds);
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
env->pc_w = 0;
env->sregI = 1;
@ -223,9 +225,12 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = avr_cpu_class_by_name;

4
target/cris/cpu-qom.h
View File

@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
/**
* CRISCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
* @vr: Version Register value.
*
* A CRIS CPU model.
@ -41,7 +41,7 @@ struct CRISCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
uint32_t vr;
};

12
target/cris/cpu.c
View File

@ -56,15 +56,17 @@ static bool cris_cpu_has_work(CPUState *cs)
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
static void cris_cpu_reset(DeviceState *dev)
static void cris_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
CRISCPU *cpu = CRIS_CPU(s);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
CPUCRISState *env = &cpu->env;
uint32_t vr;
ccc->parent_reset(dev);
if (ccc->parent_phases.hold) {
ccc->parent_phases.hold(obj);
}
vr = env->pregs[PR_VR];
memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
@ -305,11 +307,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, cris_cpu_realizefn,
&ccc->parent_realize);
device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL,
&ccc->parent_phases);
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;

12
target/hexagon/cpu.c
View File

@ -281,14 +281,16 @@ static void hexagon_restore_state_to_opc(CPUState *cs,
env->gpr[HEX_REG_PC] = data[0];
}
static void hexagon_cpu_reset(DeviceState *dev)
static void hexagon_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(dev);
CPUState *cs = CPU(obj);
HexagonCPU *cpu = HEXAGON_CPU(cs);
HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu);
CPUHexagonState *env = &cpu->env;
mcc->parent_reset(dev);
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
set_default_nan_mode(1, &env->fp_status);
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
@ -339,11 +341,13 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, hexagon_cpu_realize,
&mcc->parent_realize);
device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = hexagon_cpu_class_by_name;
cc->has_work = hexagon_cpu_has_work;

2
target/hexagon/cpu.h
View File

@ -137,7 +137,7 @@ typedef struct HexagonCPUClass {
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
} HexagonCPUClass;
struct ArchCPU {

4
target/i386/cpu-qom.h
View File

@ -42,7 +42,7 @@ typedef struct X86CPUModel X86CPUModel;
* @migration_safe: See CpuDefinitionInfo::migration_safe
* @static_model: See CpuDefinitionInfo::static
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An x86 CPU model or family.
*/
@ -67,7 +67,7 @@ struct X86CPUClass {
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};

12
target/i386/cpu.c
View File

@ -5877,9 +5877,9 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
#endif
}
static void x86_cpu_reset(DeviceState *dev)
static void x86_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
X86CPU *cpu = X86_CPU(s);
X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
CPUX86State *env = &cpu->env;
@ -5887,7 +5887,9 @@ static void x86_cpu_reset(DeviceState *dev)
uint64_t xcr0;
int i;
xcc->parent_reset(dev);
if (xcc->parent_phases.hold) {
xcc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUX86State, end_reset_fields));
@ -7111,6 +7113,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
FeatureWord w;
device_class_set_parent_realize(dc, x86_cpu_realizefn,
@ -7119,7 +7122,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
&xcc->parent_unrealize);
device_class_set_props(dc, x86_cpu_properties);
device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL,
&xcc->parent_phases);
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
cc->class_by_name = x86_cpu_class_by_name;

12
target/loongarch/cpu.c
View File

@ -450,14 +450,16 @@ void loongarch_cpu_list(void)
g_slist_free(list);
}
static void loongarch_cpu_reset(DeviceState *dev)
static void loongarch_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(dev);
CPUState *cs = CPU(obj);
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
CPULoongArchState *env = &cpu->env;
lacc->parent_reset(dev);
if (lacc->parent_phases.hold) {
lacc->parent_phases.hold(obj);
}
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
env->fcsr0 = 0x0;
@ -694,10 +696,12 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
&lacc->parent_realize);
device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL,
&lacc->parent_phases);
cc->class_by_name = loongarch_cpu_class_by_name;
cc->has_work = loongarch_cpu_has_work;

4
target/loongarch/cpu.h
View File

@ -356,7 +356,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
/**
* LoongArchCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A LoongArch CPU model.
*/
@ -366,7 +366,7 @@ struct LoongArchCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
/*

4
target/m68k/cpu-qom.h
View File

@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
/*
* M68kCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A Motorola 68k CPU model.
*/
@ -40,7 +40,7 @@ struct M68kCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};

12
target/m68k/cpu.c
View File

@ -66,16 +66,18 @@ static void m68k_unset_feature(CPUM68KState *env, int feature)
env->features &= ~BIT_ULL(feature);
}
static void m68k_cpu_reset(DeviceState *dev)
static void m68k_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
M68kCPU *cpu = M68K_CPU(s);
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);
CPUM68KState *env = &cpu->env;
floatx80 nan = floatx80_default_nan(NULL);
int i;
mcc->parent_reset(dev);
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUM68KState, end_reset_fields));
#ifdef CONFIG_SOFTMMU
@ -552,10 +554,12 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
M68kCPUClass *mcc = M68K_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, m68k_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, m68k_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;

4
target/microblaze/cpu-qom.h
View File

@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MicroBlaze CPU model.
*/
@ -40,7 +40,7 @@ struct MicroBlazeCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};

12
target/microblaze/cpu.c
View File

@ -162,14 +162,16 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
}
#endif
static void mb_cpu_reset(DeviceState *dev)
static void mb_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
CPUMBState *env = &cpu->env;
mcc->parent_reset(dev);
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUMBState, end_reset_fields));
env->res_addr = RES_ADDR_NONE;
@ -399,10 +401,12 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, mb_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;

4
target/mips/cpu-qom.h
View File

@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/**
* MIPSCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MIPS CPU model.
*/
@ -44,7 +44,7 @@ struct MIPSCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */

12
target/mips/cpu.c
View File

@ -182,14 +182,16 @@ static bool mips_cpu_has_work(CPUState *cs)
#include "cpu-defs.c.inc"
static void mips_cpu_reset(DeviceState *dev)
static void mips_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(dev);
CPUState *cs = CPU(obj);
MIPSCPU *cpu = MIPS_CPU(cs);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
CPUMIPSState *env = &cpu->env;
mcc->parent_reset(dev);
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
@ -562,10 +564,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;

12
target/nios2/cpu.c
View File

@ -57,14 +57,16 @@ static bool nios2_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
static void nios2_cpu_reset(DeviceState *dev)
static void nios2_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(dev);
CPUState *cs = CPU(obj);
Nios2CPU *cpu = NIOS2_CPU(cs);
Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
CPUNios2State *env = &cpu->env;
ncc->parent_reset(dev);
if (ncc->parent_phases.hold) {
ncc->parent_phases.hold(obj);
}
memset(env->ctrl, 0, sizeof(env->ctrl));
env->pc = cpu->reset_addr;
@ -371,11 +373,13 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, nios2_cpu_realizefn,
&ncc->parent_realize);
device_class_set_props(dc, nios2_properties);
device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, nios2_cpu_reset_hold, NULL,
&ncc->parent_phases);
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;

4
target/nios2/cpu.h
View File

@ -37,7 +37,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
/**
* Nios2CPUClass:
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A Nios2 CPU model.
*/
@ -47,7 +47,7 @@ struct Nios2CPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
#define TARGET_HAS_ICE 1

12
target/openrisc/cpu.c
View File

@ -70,13 +70,15 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
info->print_insn = print_insn_or1k;
}
static void openrisc_cpu_reset(DeviceState *dev)
static void openrisc_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
OpenRISCCPU *cpu = OPENRISC_CPU(s);
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
occ->parent_reset(dev);
if (occ->parent_phases.hold) {
occ->parent_phases.hold(obj);
}
memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
@ -229,10 +231,12 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(occ);
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
&occ->parent_realize);
device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL,
&occ->parent_phases);
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;

4
target/openrisc/cpu.h
View File

@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
/**
* OpenRISCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A OpenRISC CPU model.
*/
@ -44,7 +44,7 @@ struct OpenRISCCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
#define TARGET_INSN_START_EXTRA_WORDS 1

4
target/ppc/cpu-qom.h
View File

@ -143,7 +143,7 @@ typedef struct PPCHash64Options PPCHash64Options;
/**
* PowerPCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A PowerPC CPU model.
*/
@ -154,7 +154,7 @@ struct PowerPCCPUClass {
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
void (*parent_parse_features)(const char *type, char *str, Error **errp);
uint32_t pvr;

12
target/ppc/cpu_init.c
View File

@ -7031,16 +7031,18 @@ static bool ppc_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
static void ppc_cpu_reset(DeviceState *dev)
static void ppc_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
PowerPCCPU *cpu = POWERPC_CPU(s);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr;
int i;
pcc->parent_reset(dev);
if (pcc->parent_phases.hold) {
pcc->parent_phases.hold(obj);
}
msr = (target_ulong)0;
msr |= (target_ulong)MSR_HVB;
@ -7267,6 +7269,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, ppc_cpu_realize,
&pcc->parent_realize);
@ -7275,7 +7278,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
pcc->pvr_match = ppc_pvr_match_default;
device_class_set_props(dc, ppc_cpu_properties);
device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
&pcc->parent_phases);
cc->class_by_name = ppc_cpu_class_by_name;
cc->has_work = ppc_cpu_has_work;

12
target/riscv/cpu.c
View File

@ -519,18 +519,20 @@ static void riscv_restore_state_to_opc(CPUState *cs,
env->bins = data[1];
}
static void riscv_cpu_reset(DeviceState *dev)
static void riscv_cpu_reset_hold(Object *obj)
{
#ifndef CONFIG_USER_ONLY
uint8_t iprio;
int i, irq, rdzero;
#endif
CPUState *cs = CPU(dev);
CPUState *cs = CPU(obj);
RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPURISCVState *env = &cpu->env;
mcc->parent_reset(dev);
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
#ifndef CONFIG_USER_ONLY
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
@ -1161,11 +1163,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, riscv_cpu_realize,
&mcc->parent_realize);
device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;

4
target/riscv/cpu.h
View File

@ -395,7 +395,7 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RISCV CPU model.
*/
@ -404,7 +404,7 @@ struct RISCVCPUClass {
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
struct RISCVCPUConfig {

4
target/rx/cpu-qom.h
View File

@ -31,7 +31,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
/*
* RXCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RX CPU model.
*/
@ -41,7 +41,7 @@ struct RXCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
#endif

13
target/rx/cpu.c
View File

@ -62,14 +62,16 @@ static bool rx_cpu_has_work(CPUState *cs)
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
}
static void rx_cpu_reset(DeviceState *dev)
static void rx_cpu_reset_hold(Object *obj)
{
RXCPU *cpu = RX_CPU(dev);
RXCPU *cpu = RX_CPU(obj);
RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
CPURXState *env = &cpu->env;
uint32_t *resetvec;
rcc->parent_reset(dev);
if (rcc->parent_phases.hold) {
rcc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPURXState, end_reset_fields));
@ -215,11 +217,12 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
CPUClass *cc = CPU_CLASS(klass);
RXCPUClass *rcc = RX_CPU_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
device_class_set_parent_realize(dc, rx_cpu_realize,
&rcc->parent_realize);
device_class_set_parent_reset(dc, rx_cpu_reset,
&rcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
&rcc->parent_phases);
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;

4
target/sh4/cpu-qom.h
View File

@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
/**
* SuperHCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
* @pvr: Processor Version Register
* @prr: Processor Revision Register
* @cvr: Cache Version Register
@ -47,7 +47,7 @@ struct SuperHCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
uint32_t pvr;
uint32_t prr;

12
target/sh4/cpu.c
View File

@ -87,14 +87,16 @@ static bool superh_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
static void superh_cpu_reset(DeviceState *dev)
static void superh_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
SuperHCPU *cpu = SUPERH_CPU(s);
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
CPUSH4State *env = &cpu->env;
scc->parent_reset(dev);
if (scc->parent_phases.hold) {
scc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
@ -274,11 +276,13 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, superh_cpu_realizefn,
&scc->parent_realize);
device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
&scc->parent_phases);
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;

4
target/sparc/cpu-qom.h
View File

@ -35,7 +35,7 @@ typedef struct sparc_def_t sparc_def_t;
/**
* SPARCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A SPARC CPU model.
*/
@ -45,7 +45,7 @@ struct SPARCCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
sparc_def_t *cpu_def;
};

12
target/sparc/cpu.c
View File

@ -28,14 +28,16 @@
//#define DEBUG_FEATURES
static void sparc_cpu_reset(DeviceState *dev)
static void sparc_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
SPARCCPU *cpu = SPARC_CPU(s);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
CPUSPARCState *env = &cpu->env;
scc->parent_reset(dev);
if (scc->parent_phases.hold) {
scc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
env->cwp = 0;
@ -889,12 +891,14 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
&scc->parent_realize);
device_class_set_props(dc, sparc_cpu_properties);
device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
&scc->parent_phases);
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;

2
target/tricore/cpu-qom.h
View File

@ -32,7 +32,7 @@ struct TriCoreCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};

12
target/tricore/cpu.c
View File

@ -68,14 +68,16 @@ static void tricore_restore_state_to_opc(CPUState *cs,
env->PC = data[0];
}
static void tricore_cpu_reset(DeviceState *dev)
static void tricore_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
TriCoreCPU *cpu = TRICORE_CPU(s);
TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu);
CPUTriCoreState *env = &cpu->env;
tcc->parent_reset(dev);
if (tcc->parent_phases.hold) {
tcc->parent_phases.hold(obj);
}
cpu_state_reset(env);
}
@ -180,11 +182,13 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, tricore_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = tricore_cpu_class_by_name;
cc->has_work = tricore_cpu_has_work;

4
target/xtensa/cpu-qom.h
View File

@ -41,7 +41,7 @@ typedef struct XtensaConfig XtensaConfig;
/**
* XtensaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @parent_phases: The parent class' reset phase handlers.
* @config: The CPU core configuration.
*
* An Xtensa CPU model.
@ -52,7 +52,7 @@ struct XtensaCPUClass {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
const XtensaConfig *config;
};

12
target/xtensa/cpu.c
View File

@ -85,16 +85,18 @@ bool xtensa_abi_call0(void)
}
#endif
static void xtensa_cpu_reset(DeviceState *dev)
static void xtensa_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(dev);
CPUState *s = CPU(obj);
XtensaCPU *cpu = XTENSA_CPU(s);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
CPUXtensaState *env = &cpu->env;
bool dfpu = xtensa_option_enabled(env->config,
XTENSA_OPTION_DFP_COPROCESSOR);
xcc->parent_reset(dev);
if (xcc->parent_phases.hold) {
xcc->parent_phases.hold(obj);
}
env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
env->sregs[LITBASE] &= ~1;
@ -240,11 +242,13 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
&xcc->parent_realize);
device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL,
&xcc->parent_phases);
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;