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target/openrisc: Use identical sizes for ITLB and DTLB

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The sizes are already the same, however, we can improve things
if they are identical by design.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Richard Henderson 2018-05-22 20:18:20 -07:00 committed by Stafford Horne
parent b9bed1b9ab
commit 56c3a14156
4 changed files with 16 additions and 18 deletions
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10
target/openrisc/cpu.h
View File

@ -222,10 +222,8 @@ enum {
/* TLB size */
enum {
DTLB_SIZE = 64,
DTLB_MASK = (DTLB_SIZE-1),
ITLB_SIZE = 64,
ITLB_MASK = (ITLB_SIZE-1),
TLB_SIZE = 64,
TLB_MASK = TLB_SIZE - 1,
};
/* TLB prot */
@ -254,8 +252,8 @@ typedef struct OpenRISCTLBEntry {
#ifndef CONFIG_USER_ONLY
typedef struct CPUOpenRISCTLBContext {
OpenRISCTLBEntry itlb[ITLB_SIZE];
OpenRISCTLBEntry dtlb[DTLB_SIZE];
OpenRISCTLBEntry itlb[TLB_SIZE];
OpenRISCTLBEntry dtlb[TLB_SIZE];
int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
hwaddr *physical,

4
target/openrisc/machine.c
View File

@ -42,9 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0,
VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0,
VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
VMSTATE_END_OF_LIST()
}

4
target/openrisc/mmu.c
View File

@ -41,7 +41,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
target_ulong address, int rw, bool supervisor)
{
int vpn = address >> TARGET_PAGE_BITS;
int idx = vpn & ITLB_MASK;
int idx = vpn & TLB_MASK;
int right = 0;
uint32_t mr = cpu->env.tlb.itlb[idx].mr;
uint32_t tr = cpu->env.tlb.itlb[idx].tr;
@ -74,7 +74,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
target_ulong address, int rw, bool supervisor)
{
int vpn = address >> TARGET_PAGE_BITS;
int idx = vpn & DTLB_MASK;
int idx = vpn & TLB_MASK;
int right = 0;
uint32_t mr = cpu->env.tlb.dtlb[idx].mr;
uint32_t tr = cpu->env.tlb.dtlb[idx].tr;

16
target/openrisc/sys_helper.c
View File

@ -80,7 +80,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
env->shadow_gpr[idx / 32][idx % 32] = rb;
break;
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
mr = env->tlb.dtlb[idx].mr;
if (mr & 1) {
@ -91,7 +91,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
}
env->tlb.dtlb[idx].mr = rb;
break;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
env->tlb.dtlb[idx].tr = rb;
break;
@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
mr = env->tlb.itlb[idx].mr;
if (mr & 1) {
@ -114,7 +114,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
}
env->tlb.itlb[idx].mr = rb;
break;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
env->tlb.itlb[idx].tr = rb;
break;
@ -247,11 +247,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
idx = (spr - 1024);
return env->shadow_gpr[idx / 32][idx % 32];
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
return env->tlb.dtlb[idx].mr;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
return env->tlb.dtlb[idx].tr;
@ -263,11 +263,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
return env->tlb.itlb[idx].mr;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
return env->tlb.itlb[idx].tr;