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spapr/pci: Convert types to QEMU coding style
The QEMU coding style requires: - to typedef structured types (HACKING) - to use CamelCase for types and structure names (CODING_STYLE) Do that for PCI and Nvlink2 code. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <156701644465.505236.2850655823182656869.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Greg Kurz
David Gibson
parent
6c3829a265
commit
572ebd08b3
@ -280,7 +280,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
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unsigned int irq, max_irqs = 0;
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SpaprPhbState *phb = NULL;
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PCIDevice *pdev = NULL;
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spapr_pci_msi *msi;
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SpaprPciMsi *msi;
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int *config_addr_key;
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Error *err = NULL;
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int i;
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@ -328,7 +328,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
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return;
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}
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msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
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msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
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/* Releasing MSIs */
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if (!req_num) {
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@ -415,7 +415,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
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irq, req_num);
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/* Add MSI device to cache */
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msi = g_new(spapr_pci_msi, 1);
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msi = g_new(SpaprPciMsi, 1);
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msi->first_irq = irq;
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msi->num = req_num;
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config_addr_key = g_new(int, 1);
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@ -446,7 +446,7 @@ static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
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unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
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SpaprPhbState *phb = NULL;
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PCIDevice *pdev = NULL;
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spapr_pci_msi *msi;
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SpaprPciMsi *msi;
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/* Find SpaprPhbState */
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phb = spapr_pci_find_phb(spapr, buid);
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@ -459,7 +459,7 @@ static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
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}
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/* Find device descriptor and start IRQ */
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msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
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msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
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if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
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trace_spapr_pci_msi("Failed to return vector", config_addr);
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rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
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@ -1806,7 +1806,7 @@ static void spapr_phb_destroy_msi(gpointer opaque)
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{
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SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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spapr_pci_msi *msi = opaque;
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SpaprPciMsi *msi = opaque;
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if (!smc->legacy_irq_allocation) {
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spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
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@ -2120,7 +2120,7 @@ static const VMStateDescription vmstate_spapr_pci_lsi = {
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL),
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VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL),
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VMSTATE_END_OF_LIST()
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},
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@ -2131,9 +2131,9 @@ static const VMStateDescription vmstate_spapr_pci_msi = {
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(key, spapr_pci_msi_mig),
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VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
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VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
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VMSTATE_UINT32(key, SpaprPciMsiMig),
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VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig),
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VMSTATE_UINT32(value.num, SpaprPciMsiMig),
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VMSTATE_END_OF_LIST()
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},
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};
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@ -2165,12 +2165,12 @@ static int spapr_pci_pre_save(void *opaque)
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if (!sphb->msi_devs_num) {
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return 0;
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}
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sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num);
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sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num);
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g_hash_table_iter_init(&iter, sphb->msi);
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for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
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sphb->msi_devs[i].key = *(uint32_t *) key;
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sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
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sphb->msi_devs[i].value = *(SpaprPciMsi *) value;
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}
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return 0;
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@ -2217,10 +2217,10 @@ static const VMStateDescription vmstate_spapr_pci = {
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VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration),
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VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration),
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VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
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vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
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vmstate_spapr_pci_lsi, SpaprPciLsi),
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VMSTATE_INT32(msi_devs_num, SpaprPhbState),
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VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0,
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vmstate_spapr_pci_msi, spapr_pci_msi_mig),
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vmstate_spapr_pci_msi, SpaprPciMsiMig),
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VMSTATE_END_OF_LIST()
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},
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};
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@ -39,11 +39,7 @@
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#define SPAPR_GPU_NUMA_ID (cpu_to_be32(1))
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struct spapr_phb_pci_nvgpu_config {
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uint64_t nv2_ram_current;
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uint64_t nv2_atsd_current;
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int num; /* number of non empty (i.e. tgt!=0) entries in slots[] */
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struct spapr_phb_pci_nvgpu_slot {
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typedef struct SpaprPhbPciNvGpuSlot {
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uint64_t tgt;
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uint64_t gpa;
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unsigned numa_id;
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@ -54,12 +50,18 @@ struct spapr_phb_pci_nvgpu_config {
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PCIDevice *npdev;
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uint32_t link_speed;
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} links[NVGPU_MAX_LINKS];
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} slots[NVGPU_MAX_NUM];
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} SpaprPhbPciNvGpuSlot;
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struct SpaprPhbPciNvGpuConfig {
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uint64_t nv2_ram_current;
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uint64_t nv2_atsd_current;
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int num; /* number of non empty (i.e. tgt!=0) entries in slots[] */
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SpaprPhbPciNvGpuSlot slots[NVGPU_MAX_NUM];
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Error *errp;
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};
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static struct spapr_phb_pci_nvgpu_slot *
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spapr_nvgpu_get_slot(struct spapr_phb_pci_nvgpu_config *nvgpus, uint64_t tgt)
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static SpaprPhbPciNvGpuSlot *
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spapr_nvgpu_get_slot(SpaprPhbPciNvGpuConfig *nvgpus, uint64_t tgt)
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{
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int i;
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@ -81,13 +83,13 @@ spapr_nvgpu_get_slot(struct spapr_phb_pci_nvgpu_config *nvgpus, uint64_t tgt)
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return &nvgpus->slots[i];
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}
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static void spapr_pci_collect_nvgpu(struct spapr_phb_pci_nvgpu_config *nvgpus,
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static void spapr_pci_collect_nvgpu(SpaprPhbPciNvGpuConfig *nvgpus,
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PCIDevice *pdev, uint64_t tgt,
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MemoryRegion *mr, Error **errp)
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{
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MachineState *machine = MACHINE(qdev_get_machine());
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SpaprMachineState *spapr = SPAPR_MACHINE(machine);
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struct spapr_phb_pci_nvgpu_slot *nvslot = spapr_nvgpu_get_slot(nvgpus, tgt);
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SpaprPhbPciNvGpuSlot *nvslot = spapr_nvgpu_get_slot(nvgpus, tgt);
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if (!nvslot) {
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error_setg(errp, "Found too many GPUs per vPHB");
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@ -102,11 +104,11 @@ static void spapr_pci_collect_nvgpu(struct spapr_phb_pci_nvgpu_config *nvgpus,
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++spapr->gpu_numa_id;
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}
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static void spapr_pci_collect_nvnpu(struct spapr_phb_pci_nvgpu_config *nvgpus,
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static void spapr_pci_collect_nvnpu(SpaprPhbPciNvGpuConfig *nvgpus,
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PCIDevice *pdev, uint64_t tgt,
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MemoryRegion *mr, Error **errp)
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{
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struct spapr_phb_pci_nvgpu_slot *nvslot = spapr_nvgpu_get_slot(nvgpus, tgt);
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SpaprPhbPciNvGpuSlot *nvslot = spapr_nvgpu_get_slot(nvgpus, tgt);
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int j;
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if (!nvslot) {
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@ -138,7 +140,7 @@ static void spapr_phb_pci_collect_nvgpu(PCIBus *bus, PCIDevice *pdev,
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if (tgt) {
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Error *local_err = NULL;
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struct spapr_phb_pci_nvgpu_config *nvgpus = opaque;
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SpaprPhbPciNvGpuConfig *nvgpus = opaque;
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Object *mr_gpu = object_property_get_link(po, "nvlink2-mr[0]", NULL);
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Object *mr_npu = object_property_get_link(po, "nvlink2-atsd-mr[0]",
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NULL);
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@ -177,7 +179,7 @@ void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
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return;
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}
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sphb->nvgpus = g_new0(struct spapr_phb_pci_nvgpu_config, 1);
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sphb->nvgpus = g_new0(SpaprPhbPciNvGpuConfig, 1);
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sphb->nvgpus->nv2_ram_current = sphb->nv2_gpa_win_addr;
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sphb->nvgpus->nv2_atsd_current = sphb->nv2_atsd_win_addr;
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@ -194,7 +196,7 @@ void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
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/* Add found GPU RAM and ATSD MRs if found */
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for (i = 0, valid_gpu_num = 0; i < sphb->nvgpus->num; ++i) {
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Object *nvmrobj;
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struct spapr_phb_pci_nvgpu_slot *nvslot = &sphb->nvgpus->slots[i];
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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if (!nvslot->gpdev) {
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continue;
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@ -242,7 +244,7 @@ void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
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}
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for (i = 0; i < sphb->nvgpus->num; ++i) {
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struct spapr_phb_pci_nvgpu_slot *nvslot = &sphb->nvgpus->slots[i];
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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Object *nv_mrobj = object_property_get_link(OBJECT(nvslot->gpdev),
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"nvlink2-mr[0]", NULL);
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@ -276,7 +278,7 @@ void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
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}
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for (i = 0; (i < sphb->nvgpus->num) && (atsdnum < ARRAY_SIZE(atsd)); ++i) {
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struct spapr_phb_pci_nvgpu_slot *nvslot = &sphb->nvgpus->slots[i];
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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if (!nvslot->gpdev) {
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continue;
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@ -354,7 +356,7 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
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/* Add memory nodes for GPU RAM and mark them unusable */
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for (i = 0; i < sphb->nvgpus->num; ++i) {
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struct spapr_phb_pci_nvgpu_slot *nvslot = &sphb->nvgpus->slots[i];
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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Object *nv_mrobj = object_property_get_link(OBJECT(nvslot->gpdev),
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"nvlink2-mr[0]", NULL);
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uint32_t associativity[] = {
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@ -398,7 +400,7 @@ void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
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}
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for (i = 0; i < sphb->nvgpus->num; ++i) {
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struct spapr_phb_pci_nvgpu_slot *nvslot = &sphb->nvgpus->slots[i];
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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/* Skip "slot" without attached GPU */
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if (!nvslot->gpdev) {
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@ -34,15 +34,21 @@
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typedef struct SpaprPhbState SpaprPhbState;
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typedef struct spapr_pci_msi {
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typedef struct SpaprPciMsi {
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uint32_t first_irq;
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uint32_t num;
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} spapr_pci_msi;
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} SpaprPciMsi;
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typedef struct spapr_pci_msi_mig {
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typedef struct SpaprPciMsiMig {
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uint32_t key;
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spapr_pci_msi value;
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} spapr_pci_msi_mig;
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SpaprPciMsi value;
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} SpaprPciMsiMig;
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typedef struct SpaprPciLsi {
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uint32_t irq;
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} SpaprPciLsi;
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typedef struct SpaprPhbPciNvGpuConfig SpaprPhbPciNvGpuConfig;
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struct SpaprPhbState {
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PCIHostState parent_obj;
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@ -63,14 +69,12 @@ struct SpaprPhbState {
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AddressSpace iommu_as;
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MemoryRegion iommu_root;
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struct spapr_pci_lsi {
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uint32_t irq;
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} lsi_table[PCI_NUM_PINS];
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SpaprPciLsi lsi_table[PCI_NUM_PINS];
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GHashTable *msi;
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/* Temporary cache for migration purposes */
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int32_t msi_devs_num;
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spapr_pci_msi_mig *msi_devs;
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SpaprPciMsiMig *msi_devs;
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QLIST_ENTRY(SpaprPhbState) list;
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@ -89,7 +93,7 @@ struct SpaprPhbState {
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hwaddr mig_io_win_addr, mig_io_win_size;
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hwaddr nv2_gpa_win_addr;
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hwaddr nv2_atsd_win_addr;
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struct spapr_phb_pci_nvgpu_config *nvgpus;
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SpaprPhbPciNvGpuConfig *nvgpus;
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};
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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