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hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines

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Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-08-30 15:35:15 +10:00
parent f436ecc315
commit 57a3a62265
3 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/riscv/opentitan.c
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@ -183,6 +183,9 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
0, qdev_get_gpio_in(DEVICE(&s->plic), 0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_TIMER_TIMEREXPIRED0_0)); IBEX_TIMER_TIMEREXPIRED0_0));
qdev_connect_gpio_out(DEVICE(&s->timer), 0,
qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
IRQ_M_TIMER));
create_unimplemented_device("riscv.lowrisc.ibex.gpio", create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);

17
hw/timer/ibex_timer.c
View File

@ -77,7 +77,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
/* /*
* If the mtimecmp was in the past raise the interrupt now. * If the mtimecmp was in the past raise the interrupt now.
*/ */
riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); qemu_irq_raise(s->m_timer_irq);
if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true); qemu_set_irq(s->irq, true);
@ -86,7 +86,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
} }
/* Setup a timer to trigger the interrupt in the future */ /* Setup a timer to trigger the interrupt in the future */
riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0)); qemu_irq_lower(s->m_timer_irq);
qemu_set_irq(s->irq, false); qemu_set_irq(s->irq, false);
diff = cpu->env.timecmp - now; diff = cpu->env.timecmp - now;
@ -106,10 +106,8 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
static void ibex_timer_cb(void *opaque) static void ibex_timer_cb(void *opaque)
{ {
IbexTimerState *s = opaque; IbexTimerState *s = opaque;
CPUState *cs = qemu_get_cpu(0);
RISCVCPU *cpu = RISCV_CPU(cs);
riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); qemu_irq_raise(s->m_timer_irq);
if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true); qemu_set_irq(s->irq, true);
@ -280,12 +278,21 @@ static void ibex_timer_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
} }
static void ibex_timer_realize(DeviceState *dev, Error **errp)
{
IbexTimerState *s = IBEX_TIMER(dev);
qdev_init_gpio_out(dev, &s->m_timer_irq, 1);
}
static void ibex_timer_class_init(ObjectClass *klass, void *data) static void ibex_timer_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = ibex_timer_reset; dc->reset = ibex_timer_reset;
dc->vmsd = &vmstate_ibex_timer; dc->vmsd = &vmstate_ibex_timer;
dc->realize = ibex_timer_realize;
device_class_set_props(dc, ibex_timer_properties); device_class_set_props(dc, ibex_timer_properties);
} }

2
include/hw/timer/ibex_timer.h
View File

@ -48,5 +48,7 @@ struct IbexTimerState {
uint32_t timebase_freq; uint32_t timebase_freq;
qemu_irq irq; qemu_irq irq;
qemu_irq m_timer_irq;
}; };
#endif /* HW_IBEX_TIMER_H */ #endif /* HW_IBEX_TIMER_H */