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Hexagon (target/hexagon) TCG generation
Include the generated files and set up the data structures Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-27-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson
Richard Henderson
parent
471d4b2dc6
commit
57acfcdeb2
331
target/hexagon/genptr.c
Normal file
331
target/hexagon/genptr.c
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define QEMU_GENERATE
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "internal.h"
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#include "tcg/tcg-op.h"
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#include "insn.h"
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#include "opcodes.h"
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#include "translate.h"
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#include "macros.h"
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#include "gen_tcg.h"
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static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
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{
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tcg_gen_mov_tl(pred, hex_pred[num]);
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return pred;
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}
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static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
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{
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TCGv one = tcg_const_tl(1);
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TCGv zero = tcg_const_tl(0);
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TCGv slot_mask = tcg_temp_new();
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tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
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val, hex_new_value[rnum]);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero,
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one, hex_reg_written[rnum]);
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#endif
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tcg_temp_free(one);
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tcg_temp_free(zero);
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tcg_temp_free(slot_mask);
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}
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static inline void gen_log_reg_write(int rnum, TCGv val)
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{
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tcg_gen_mov_tl(hex_new_value[rnum], val);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum], 1);
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#endif
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}
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static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
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{
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TCGv val32 = tcg_temp_new();
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TCGv one = tcg_const_tl(1);
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TCGv zero = tcg_const_tl(0);
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TCGv slot_mask = tcg_temp_new();
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tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
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/* Low word */
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tcg_gen_extrl_i64_i32(val32, val);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
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val32, hex_new_value[rnum]);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum],
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slot_mask, zero,
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one, hex_reg_written[rnum]);
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#endif
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/* High word */
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tcg_gen_extrh_i64_i32(val32, val);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
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slot_mask, zero,
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val32, hex_new_value[rnum + 1]);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum + 1],
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slot_mask, zero,
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one, hex_reg_written[rnum + 1]);
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#endif
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tcg_temp_free(val32);
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tcg_temp_free(one);
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tcg_temp_free(zero);
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tcg_temp_free(slot_mask);
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}
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static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
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{
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/* Low word */
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tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum], 1);
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#endif
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/* High word */
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tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
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#if HEX_DEBUG
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
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#endif
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}
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static inline void gen_log_pred_write(int pnum, TCGv val)
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{
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TCGv zero = tcg_const_tl(0);
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TCGv base_val = tcg_temp_new();
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TCGv and_val = tcg_temp_new();
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TCGv pred_written = tcg_temp_new();
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/* Multiple writes to the same preg are and'ed together */
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tcg_gen_andi_tl(base_val, val, 0xff);
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tcg_gen_and_tl(and_val, base_val, hex_new_pred_value[pnum]);
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tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pnum);
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tcg_gen_movcond_tl(TCG_COND_NE, hex_new_pred_value[pnum],
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pred_written, zero,
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and_val, base_val);
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
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tcg_temp_free(zero);
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tcg_temp_free(base_val);
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tcg_temp_free(and_val);
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tcg_temp_free(pred_written);
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}
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static inline void gen_read_p3_0(TCGv control_reg)
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{
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tcg_gen_movi_tl(control_reg, 0);
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for (int i = 0; i < NUM_PREGS; i++) {
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tcg_gen_deposit_tl(control_reg, control_reg, hex_pred[i], i * 8, 8);
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}
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}
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/*
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* Certain control registers require special handling on read
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* HEX_REG_P3_0 aliased to the predicate registers
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* -> concat the 4 predicate registers together
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* HEX_REG_PC actual value stored in DisasContext
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* -> assign from ctx->base.pc_next
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* HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
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* -> add current TB changes to existing reg value
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*/
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static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
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TCGv dest)
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{
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if (reg_num == HEX_REG_P3_0) {
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gen_read_p3_0(dest);
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} else if (reg_num == HEX_REG_PC) {
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tcg_gen_movi_tl(dest, ctx->base.pc_next);
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} else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
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tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_PKT_CNT],
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ctx->num_packets);
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} else if (reg_num == HEX_REG_QEMU_INSN_CNT) {
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tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT],
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ctx->num_insns);
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} else {
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tcg_gen_mov_tl(dest, hex_gpr[reg_num]);
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}
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}
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static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
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TCGv_i64 dest)
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{
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if (reg_num == HEX_REG_P3_0) {
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TCGv p3_0 = tcg_temp_new();
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gen_read_p3_0(p3_0);
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tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
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tcg_temp_free(p3_0);
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} else if (reg_num == HEX_REG_PC - 1) {
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TCGv pc = tcg_const_tl(ctx->base.pc_next);
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tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc);
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tcg_temp_free(pc);
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} else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
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TCGv pkt_cnt = tcg_temp_new();
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TCGv insn_cnt = tcg_temp_new();
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tcg_gen_addi_tl(pkt_cnt, hex_gpr[HEX_REG_QEMU_PKT_CNT],
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ctx->num_packets);
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tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT],
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ctx->num_insns);
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tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt);
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tcg_temp_free(pkt_cnt);
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tcg_temp_free(insn_cnt);
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} else {
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tcg_gen_concat_i32_i64(dest,
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hex_gpr[reg_num],
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hex_gpr[reg_num + 1]);
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}
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}
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static inline void gen_write_p3_0(TCGv control_reg)
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{
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for (int i = 0; i < NUM_PREGS; i++) {
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tcg_gen_extract_tl(hex_pred[i], control_reg, i * 8, 8);
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}
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}
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/*
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* Certain control registers require special handling on write
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* HEX_REG_P3_0 aliased to the predicate registers
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* -> break the value across 4 predicate registers
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* HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
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* -> clear the changes
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*/
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static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
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TCGv val)
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{
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if (reg_num == HEX_REG_P3_0) {
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gen_write_p3_0(val);
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} else {
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gen_log_reg_write(reg_num, val);
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ctx_log_reg_write(ctx, reg_num);
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if (reg_num == HEX_REG_QEMU_PKT_CNT) {
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ctx->num_packets = 0;
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}
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if (reg_num == HEX_REG_QEMU_INSN_CNT) {
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ctx->num_insns = 0;
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}
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}
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}
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static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
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TCGv_i64 val)
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{
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if (reg_num == HEX_REG_P3_0) {
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TCGv val32 = tcg_temp_new();
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tcg_gen_extrl_i64_i32(val32, val);
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gen_write_p3_0(val32);
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tcg_gen_extrh_i64_i32(val32, val);
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gen_log_reg_write(reg_num + 1, val32);
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tcg_temp_free(val32);
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ctx_log_reg_write(ctx, reg_num + 1);
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} else {
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gen_log_reg_write_pair(reg_num, val);
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ctx_log_reg_write_pair(ctx, reg_num);
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if (reg_num == HEX_REG_QEMU_PKT_CNT) {
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ctx->num_packets = 0;
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ctx->num_insns = 0;
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}
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}
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}
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static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
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{
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tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
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tcg_gen_mov_tl(hex_llsc_addr, vaddr);
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tcg_gen_mov_tl(hex_llsc_val, dest);
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}
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static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
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{
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tcg_gen_qemu_ld64(dest, vaddr, mem_index);
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tcg_gen_mov_tl(hex_llsc_addr, vaddr);
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tcg_gen_mov_i64(hex_llsc_val_i64, dest);
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}
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static inline void gen_store_conditional4(CPUHexagonState *env,
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DisasContext *ctx, int prednum,
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TCGv pred, TCGv vaddr, TCGv src)
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{
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TCGLabel *fail = gen_new_label();
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TCGLabel *done = gen_new_label();
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TCGv one, zero, tmp;
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tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
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one = tcg_const_tl(0xff);
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zero = tcg_const_tl(0);
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tmp = tcg_temp_new();
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tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
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ctx->mem_idx, MO_32);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_pred[prednum], tmp, hex_llsc_val,
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one, zero);
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tcg_temp_free(one);
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tcg_temp_free(zero);
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tcg_temp_free(tmp);
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tcg_gen_br(done);
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gen_set_label(fail);
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tcg_gen_movi_tl(pred, 0);
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gen_set_label(done);
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tcg_gen_movi_tl(hex_llsc_addr, ~0);
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}
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static inline void gen_store_conditional8(CPUHexagonState *env,
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DisasContext *ctx, int prednum,
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TCGv pred, TCGv vaddr, TCGv_i64 src)
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{
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TCGLabel *fail = gen_new_label();
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TCGLabel *done = gen_new_label();
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TCGv_i64 one, zero, tmp;
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tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
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one = tcg_const_i64(0xff);
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zero = tcg_const_i64(0);
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tmp = tcg_temp_new_i64();
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tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src,
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ctx->mem_idx, MO_64);
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tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
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one, zero);
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tcg_gen_extrl_i64_i32(hex_pred[prednum], tmp);
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tcg_temp_free_i64(one);
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tcg_temp_free_i64(zero);
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tcg_temp_free_i64(tmp);
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tcg_gen_br(done);
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gen_set_label(fail);
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tcg_gen_movi_tl(pred, 0);
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gen_set_label(done);
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tcg_gen_movi_tl(hex_llsc_addr, ~0);
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}
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#include "tcg_funcs_generated.c.inc"
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#include "tcg_func_table_generated.c.inc"
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25
target/hexagon/genptr.h
Normal file
25
target/hexagon/genptr.h
Normal file
@ -0,0 +1,25 @@
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_GENPTR_H
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#define HEXAGON_GENPTR_H
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#include "insn.h"
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extern const SemanticInsn opcode_genptr[];
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#endif
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