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tcg-sparc: Fix and enable direct TB chaining.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -132,9 +132,10 @@ static inline void tlb_flush(CPUArchState *env, int flush_global)
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#define CODE_GEN_AVG_BLOCK_SIZE 64
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#endif
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#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
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#define USE_DIRECT_JUMP
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#elif defined(CONFIG_TCG_INTERPRETER)
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#if defined(__arm__) || defined(_ARCH_PPC) \
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|| defined(__x86_64__) || defined(__i386__) \
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|| defined(__sparc__) \
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|| defined(CONFIG_TCG_INTERPRETER)
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#define USE_DIRECT_JUMP
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#endif
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@ -244,6 +245,8 @@ static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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#endif
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}
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#elif defined(__sparc__)
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void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
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#else
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#error tb_set_jmp_target1 is missing
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#endif
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@ -1072,10 +1072,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_goto_tb:
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if (s->tb_jmp_offset) {
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/* direct jump method */
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tcg_out_sethi(s, TCG_REG_T1, args[0] & 0xffffe000);
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_T1) |
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INSN_IMM13((args[0] & 0x1fff)));
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uint32_t old_insn = *(uint32_t *)s->code_ptr;
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s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
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/* Make sure to preserve links during retranslation. */
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tcg_out32(s, CALL | (old_insn & ~INSN_OP(-1)));
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} else {
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/* indirect jump method */
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tcg_out_ld_ptr(s, TCG_REG_T1,
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@ -1595,3 +1595,18 @@ void tcg_register_jit(void *buf, size_t buf_size)
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tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
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}
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void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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{
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uint32_t *ptr = (uint32_t *)jmp_addr;
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tcg_target_long disp = (tcg_target_long)(addr - jmp_addr) >> 2;
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/* We can reach the entire address space for 32-bit. For 64-bit
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the code_gen_buffer can't be larger than 2GB. */
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if (TCG_TARGET_REG_BITS == 64 && !check_fit_tl(disp, 30)) {
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tcg_abort();
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}
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*ptr = CALL | (disp & 0x3fffffff);
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flush_icache_range(jmp_addr, jmp_addr + 4);
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}
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