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https://github.com/xemu-project/xemu.git
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exec: Make stw_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
parent
2198a12143
commit
5ce5944dc0
20
exec.c
20
exec.c
@ -1628,7 +1628,7 @@ static void watch_mem_write(void *opaque, hwaddr addr,
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stb_phys(addr, val);
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break;
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case 2:
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stw_phys(addr, val);
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stw_phys(&address_space_memory, addr, val);
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break;
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case 4:
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stl_phys(&address_space_memory, addr, val);
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@ -2628,7 +2628,8 @@ void stb_phys(hwaddr addr, uint32_t val)
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}
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/* warning: addr must be aligned */
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static inline void stw_phys_internal(hwaddr addr, uint32_t val,
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static inline void stw_phys_internal(AddressSpace *as,
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hwaddr addr, uint32_t val,
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enum device_endian endian)
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{
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uint8_t *ptr;
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@ -2636,8 +2637,7 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
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hwaddr l = 2;
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hwaddr addr1;
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mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
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true);
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mr = address_space_translate(as, addr, &addr1, &l, true);
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if (l < 2 || !memory_access_is_direct(mr, true)) {
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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@ -2668,19 +2668,19 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
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}
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}
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void stw_phys(hwaddr addr, uint32_t val)
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void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
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stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN);
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}
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void stw_le_phys(hwaddr addr, uint32_t val)
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void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
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stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN);
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}
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void stw_be_phys(hwaddr addr, uint32_t val)
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void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
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stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN);
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}
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/* XXX: optimize */
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@ -89,7 +89,7 @@ static inline void
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vmw_shmem_st16(hwaddr addr, uint16_t value)
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{
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VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
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stw_le_phys(addr, value);
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stw_le_phys(&address_space_memory, addr, value);
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}
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static inline uint32_t
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@ -65,7 +65,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
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for (i = 0; i < 6; i++) {
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stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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}
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stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
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stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
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stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
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stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
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stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
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@ -570,7 +570,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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stb_phys(addr, val);
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return H_SUCCESS;
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case 2:
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stw_phys(addr, val);
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stw_phys(cs->as, addr, val);
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return H_SUCCESS;
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case 4:
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stl_phys(cs->as, addr, val);
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@ -635,7 +635,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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stb_phys(dst, tmp);
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break;
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case 1:
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stw_phys(dst, tmp);
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stw_phys(cs->as, dst, tmp);
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break;
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case 2:
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stl_phys(cs->as, dst, tmp);
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@ -680,7 +680,8 @@ static void css_update_chnmon(SubchDev *sch)
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count = lduw_phys(&address_space_memory,
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channel_subsys->chnmon_area + offset);
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count++;
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stw_phys(channel_subsys->chnmon_area + offset, count);
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stw_phys(&address_space_memory,
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channel_subsys->chnmon_area + offset, count);
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}
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}
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@ -77,10 +77,10 @@ void s390_virtio_reset_idx(VirtIOS390Device *dev)
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for (i = 0; i < num_vq; i++) {
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idx_addr = virtio_queue_get_avail_addr(dev->vdev, i) +
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VIRTIO_VRING_AVAIL_IDX_OFFS;
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stw_phys(idx_addr, 0);
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stw_phys(&address_space_memory, idx_addr, 0);
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idx_addr = virtio_queue_get_used_addr(dev->vdev, i) +
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VIRTIO_VRING_USED_IDX_OFFS;
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stw_phys(idx_addr, 0);
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stw_phys(&address_space_memory, idx_addr, 0);
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}
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}
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@ -380,7 +380,9 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
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virtio_queue_set_vector(dev->vdev, i, i);
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stq_be_phys(&address_space_memory,
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vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
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stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM, virtio_queue_get_num(dev->vdev, i));
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stw_be_phys(&address_space_memory,
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vq + VIRTIO_VQCONFIG_OFFS_NUM,
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virtio_queue_get_num(dev->vdev, i));
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}
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cur_offs = dev->dev_offs;
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@ -474,7 +474,8 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
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vq_config.index = lduw_phys(&address_space_memory, ccw.cda);
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vq_config.num_max = virtio_queue_get_num(vdev,
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vq_config.index);
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stw_phys(ccw.cda + sizeof(vq_config.index), vq_config.num_max);
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stw_phys(&address_space_memory,
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ccw.cda + sizeof(vq_config.index), vq_config.num_max);
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sch->curr_status.scsw.count = ccw.count - sizeof(vq_config);
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ret = 0;
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}
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@ -319,7 +319,7 @@ static void r2d_init(QEMUMachineInitArgs *args)
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/* initialization which should be done by firmware */
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stl_phys(&address_space_memory, SH7750_BCR1, 1<<3); /* cs3 SDRAM */
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stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
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stw_phys(&address_space_memory, SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
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reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
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}
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@ -180,21 +180,23 @@ static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
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{
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hwaddr pa;
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pa = vq->vring.used + offsetof(VRingUsed, idx);
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stw_phys(pa, val);
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stw_phys(&address_space_memory, pa, val);
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}
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static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
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{
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hwaddr pa;
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pa = vq->vring.used + offsetof(VRingUsed, flags);
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stw_phys(pa, lduw_phys(&address_space_memory, pa) | mask);
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stw_phys(&address_space_memory,
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pa, lduw_phys(&address_space_memory, pa) | mask);
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}
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static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
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{
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hwaddr pa;
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pa = vq->vring.used + offsetof(VRingUsed, flags);
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stw_phys(pa, lduw_phys(&address_space_memory, pa) & ~mask);
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stw_phys(&address_space_memory,
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pa, lduw_phys(&address_space_memory, pa) & ~mask);
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}
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static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
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@ -204,7 +206,7 @@ static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
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return;
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}
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pa = vq->vring.used + offsetof(VRingUsed, ring[vq->vring.num]);
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stw_phys(pa, val);
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stw_phys(&address_space_memory, pa, val);
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}
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void virtio_queue_set_notification(VirtQueue *vq, int enable)
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@ -91,8 +91,8 @@ uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
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uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
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uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
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void stb_phys(hwaddr addr, uint32_t val);
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void stw_le_phys(hwaddr addr, uint32_t val);
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void stw_be_phys(hwaddr addr, uint32_t val);
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void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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@ -103,7 +103,7 @@ uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
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uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
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uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
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void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
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void stw_phys(hwaddr addr, uint32_t val);
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void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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#endif
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@ -60,8 +60,8 @@ void do_smm_enter(X86CPU *cpu)
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for (i = 0; i < 6; i++) {
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dt = &env->segs[i];
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offset = 0x7e00 + i * 16;
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stw_phys(sm_state + offset, dt->selector);
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stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
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stw_phys(cs->as, sm_state + offset, dt->selector);
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stw_phys(cs->as, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
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stl_phys(cs->as, sm_state + offset + 4, dt->limit);
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stq_phys(cs->as, sm_state + offset + 8, dt->base);
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}
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@ -69,18 +69,18 @@ void do_smm_enter(X86CPU *cpu)
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stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base);
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stl_phys(cs->as, sm_state + 0x7e64, env->gdt.limit);
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stw_phys(sm_state + 0x7e70, env->ldt.selector);
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stw_phys(cs->as, sm_state + 0x7e70, env->ldt.selector);
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stq_phys(cs->as, sm_state + 0x7e78, env->ldt.base);
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stl_phys(cs->as, sm_state + 0x7e74, env->ldt.limit);
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stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
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stw_phys(cs->as, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
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stq_phys(cs->as, sm_state + 0x7e88, env->idt.base);
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stl_phys(cs->as, sm_state + 0x7e84, env->idt.limit);
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stw_phys(sm_state + 0x7e90, env->tr.selector);
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stw_phys(cs->as, sm_state + 0x7e90, env->tr.selector);
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stq_phys(cs->as, sm_state + 0x7e98, env->tr.base);
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stl_phys(cs->as, sm_state + 0x7e94, env->tr.limit);
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stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
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stw_phys(cs->as, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
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stq_phys(cs->as, sm_state + 0x7ed0, env->efer);
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@ -89,13 +89,13 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
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const SegmentCache *sc)
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{
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CPUState *cs = ENV_GET_CPU(env);
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stw_phys(addr + offsetof(struct vmcb_seg, selector),
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stw_phys(cs->as, addr + offsetof(struct vmcb_seg, selector),
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sc->selector);
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stq_phys(cs->as, addr + offsetof(struct vmcb_seg, base),
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sc->base);
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stl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit),
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sc->limit);
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stw_phys(addr + offsetof(struct vmcb_seg, attrib),
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stw_phys(cs->as, addr + offsetof(struct vmcb_seg, attrib),
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((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
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}
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@ -1043,7 +1043,8 @@ void HELPER(ptlb)(CPUS390XState *env)
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/* store using real address */
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void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1)
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{
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stw_phys(get_address(env, 0, 0, addr), (uint32_t)v1);
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CPUState *cs = ENV_GET_CPU(env);
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stw_phys(cs->as, get_address(env, 0, 0, addr), (uint32_t)v1);
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}
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/* load real address */
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@ -1015,7 +1015,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
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stb_phys(addr, val);
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break;
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case 2:
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stw_phys(addr, val);
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stw_phys(cs->as, addr, val);
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break;
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case 4:
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default:
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@ -1035,7 +1035,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
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| ((hwaddr)(asi & 0xf) << 32), val);
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break;
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case 2:
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stw_phys((hwaddr)addr
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stw_phys(cs->as, (hwaddr)addr
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| ((hwaddr)(asi & 0xf) << 32), val);
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break;
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case 4:
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@ -1814,7 +1814,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
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stb_phys(addr, val);
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break;
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case 2:
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stw_phys(addr, val);
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stw_phys(cs->as, addr, val);
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break;
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case 4:
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stl_phys(cs->as, addr, val);
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