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vfio/pci: Cleanup Nvidia 0x3d0 quirk

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The Nvidia 0x3d0 quirk makes use of a two separate registers and gives
us our first chance to make use of separate memory regions for each to
simplify the code a bit.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
Alex Williamson 2015-09-23 13:04:47 -06:00
parent b946d28611
commit 6029a424be
2 changed files with 111 additions and 68 deletions
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172
hw/vfio/pci-quirks.c
View File

@ -390,76 +390,121 @@ static void vfio_probe_ati_bar2_4000_quirk(VFIOPCIDevice *vdev, int nr)
* through 0x3d0. This quirk doesn't seem to be necessary on newer cards * through 0x3d0. This quirk doesn't seem to be necessary on newer cards
* that use the I/O port BAR5 window but it doesn't hurt to leave it. * that use the I/O port BAR5 window but it doesn't hurt to leave it.
*/ */
enum { typedef enum {NONE = 0, SELECT, WINDOW, READ, WRITE} VFIONvidia3d0State;
NV_3D0_NONE = 0, static const char *nv3d0_states[] = { "NONE", "SELECT",
NV_3D0_SELECT, "WINDOW", "READ", "WRITE" };
NV_3D0_WINDOW,
NV_3D0_READ, typedef struct VFIONvidia3d0Quirk {
NV_3D0_WRITE, VFIOPCIDevice *vdev;
VFIONvidia3d0State state;
uint32_t offset;
} VFIONvidia3d0Quirk;
static uint64_t vfio_nvidia_3d4_quirk_read(void *opaque,
hwaddr addr, unsigned size)
{
VFIONvidia3d0Quirk *quirk = opaque;
VFIOPCIDevice *vdev = quirk->vdev;
quirk->state = NONE;
return vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
addr + 0x14, size);
}
static void vfio_nvidia_3d4_quirk_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
VFIONvidia3d0Quirk *quirk = opaque;
VFIOPCIDevice *vdev = quirk->vdev;
VFIONvidia3d0State old_state = quirk->state;
quirk->state = NONE;
switch (data) {
case 0x338:
if (old_state == NONE) {
quirk->state = SELECT;
trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
nv3d0_states[quirk->state]);
}
break;
case 0x538:
if (old_state == WINDOW) {
quirk->state = READ;
trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
nv3d0_states[quirk->state]);
}
break;
case 0x738:
if (old_state == WINDOW) {
quirk->state = WRITE;
trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
nv3d0_states[quirk->state]);
}
break;
}
vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
addr + 0x14, data, size);
}
static const MemoryRegionOps vfio_nvidia_3d4_quirk = {
.read = vfio_nvidia_3d4_quirk_read,
.write = vfio_nvidia_3d4_quirk_write,
.endianness = DEVICE_LITTLE_ENDIAN,
}; };
static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque, static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque,
hwaddr addr, unsigned size) hwaddr addr, unsigned size)
{ {
VFIOLegacyQuirk *quirk = opaque; VFIONvidia3d0Quirk *quirk = opaque;
VFIOPCIDevice *vdev = quirk->vdev; VFIOPCIDevice *vdev = quirk->vdev;
PCIDevice *pdev = &vdev->pdev; VFIONvidia3d0State old_state = quirk->state;
uint64_t data = vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI], uint64_t data = vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
addr + quirk->data.base_offset, size); addr + 0x10, size);
if (quirk->data.flags == NV_3D0_READ && addr == quirk->data.data_offset) { quirk->state = NONE;
data = vfio_pci_read_config(pdev, quirk->data.address_val, size);
trace_vfio_nvidia_3d0_quirk_read(size, data); if (old_state == READ &&
(quirk->offset & ~(PCI_CONFIG_SPACE_SIZE - 1)) == 0x1800) {
uint8_t offset = quirk->offset & (PCI_CONFIG_SPACE_SIZE - 1);
data = vfio_pci_read_config(&vdev->pdev, offset, size);
trace_vfio_quirk_nvidia_3d0_read(vdev->vbasedev.name,
offset, size, data);
} }
quirk->data.flags = NV_3D0_NONE;
return data; return data;
} }
static void vfio_nvidia_3d0_quirk_write(void *opaque, hwaddr addr, static void vfio_nvidia_3d0_quirk_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size) uint64_t data, unsigned size)
{ {
VFIOLegacyQuirk *quirk = opaque; VFIONvidia3d0Quirk *quirk = opaque;
VFIOPCIDevice *vdev = quirk->vdev; VFIOPCIDevice *vdev = quirk->vdev;
PCIDevice *pdev = &vdev->pdev; VFIONvidia3d0State old_state = quirk->state;
switch (quirk->data.flags) { quirk->state = NONE;
case NV_3D0_NONE:
if (addr == quirk->data.address_offset && data == 0x338) { if (old_state == SELECT) {
quirk->data.flags = NV_3D0_SELECT; quirk->offset = (uint32_t)data;
} quirk->state = WINDOW;
break; trace_vfio_quirk_nvidia_3d0_state(vdev->vbasedev.name,
case NV_3D0_SELECT: nv3d0_states[quirk->state]);
quirk->data.flags = NV_3D0_NONE; } else if (old_state == WRITE) {
if (addr == quirk->data.data_offset && if ((quirk->offset & ~(PCI_CONFIG_SPACE_SIZE - 1)) == 0x1800) {
(data & ~quirk->data.address_mask) == quirk->data.address_match) { uint8_t offset = quirk->offset & (PCI_CONFIG_SPACE_SIZE - 1);
quirk->data.flags = NV_3D0_WINDOW;
quirk->data.address_val = data & quirk->data.address_mask; vfio_pci_write_config(&vdev->pdev, offset, data, size);
} trace_vfio_quirk_nvidia_3d0_write(vdev->vbasedev.name,
break; offset, data, size);
case NV_3D0_WINDOW:
quirk->data.flags = NV_3D0_NONE;
if (addr == quirk->data.address_offset) {
if (data == 0x538) {
quirk->data.flags = NV_3D0_READ;
} else if (data == 0x738) {
quirk->data.flags = NV_3D0_WRITE;
}
}
break;
case NV_3D0_WRITE:
quirk->data.flags = NV_3D0_NONE;
if (addr == quirk->data.data_offset) {
vfio_pci_write_config(pdev, quirk->data.address_val, data, size);
trace_vfio_nvidia_3d0_quirk_write(data, size);
return; return;
} }
break;
} }
vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI], vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI],
addr + quirk->data.base_offset, data, size); addr + 0x10, data, size);
} }
static const MemoryRegionOps vfio_nvidia_3d0_quirk = { static const MemoryRegionOps vfio_nvidia_3d0_quirk = {
@ -470,37 +515,34 @@ static const MemoryRegionOps vfio_nvidia_3d0_quirk = {
static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice *vdev) static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice *vdev)
{ {
PCIDevice *pdev = &vdev->pdev;
VFIOQuirk *quirk; VFIOQuirk *quirk;
VFIOLegacyQuirk *legacy; VFIONvidia3d0Quirk *data;
if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA || if (!vfio_pci_is(vdev, PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID) ||
!vdev->bars[1].region.size) { !vdev->bars[1].region.size) {
return; return;
} }
quirk = g_malloc0(sizeof(*quirk)); quirk = g_malloc0(sizeof(*quirk));
quirk->data = legacy = g_malloc0(sizeof(*legacy)); quirk->data = data = g_malloc0(sizeof(*data));
quirk->mem = legacy->mem = g_malloc0_n(sizeof(MemoryRegion), 1); quirk->mem = g_malloc0_n(sizeof(MemoryRegion), 2);
quirk->nr_mem = 1; quirk->nr_mem = 2;
legacy->vdev = vdev; data->vdev = vdev;
legacy->data.base_offset = 0x10;
legacy->data.address_offset = 4;
legacy->data.address_size = 2;
legacy->data.address_match = 0x1800;
legacy->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1;
legacy->data.data_offset = 0;
legacy->data.data_size = 4;
memory_region_init_io(quirk->mem, OBJECT(vdev), &vfio_nvidia_3d0_quirk, memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_nvidia_3d4_quirk,
legacy, "vfio-nvidia-3d0-quirk", 6); data, "vfio-nvidia-3d4-quirk", 2);
memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem, memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
legacy->data.base_offset, quirk->mem); 0x14 /* 0x3c0 + 0x14 */, &quirk->mem[0]);
memory_region_init_io(&quirk->mem[1], OBJECT(vdev), &vfio_nvidia_3d0_quirk,
data, "vfio-nvidia-3d0-quirk", 2);
memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem,
0x10 /* 0x3c0 + 0x10 */, &quirk->mem[1]);
QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks, QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks,
quirk, next); quirk, next);
trace_vfio_vga_probe_nvidia_3d0_quirk(vdev->vbasedev.name); trace_vfio_quirk_nvidia_3d0_probe(vdev->vbasedev.name);
} }
/* /*

7
trace-events
View File

@ -1557,9 +1557,6 @@ vfio_rtl8168_quirk_write(const char *name, uint64_t val) "%s [address]: 0x%"PRIx
vfio_rtl8168_quirk_msix(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table write[0x%x]: 0x%"PRIx64 vfio_rtl8168_quirk_msix(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table write[0x%x]: 0x%"PRIx64
vfio_rtl8168_quirk_enable(const char *name) "%s" vfio_rtl8168_quirk_enable(const char *name) "%s"
vfio_probe_ati_bar2_4000_quirk(const char *name) "Enabled ATI/AMD BAR2 0x4000 quirk for device %s" vfio_probe_ati_bar2_4000_quirk(const char *name) "Enabled ATI/AMD BAR2 0x4000 quirk for device %s"
vfio_nvidia_3d0_quirk_read(int size, uint64_t data) " (0x3d0, %d) = 0x%"PRIx64
vfio_nvidia_3d0_quirk_write(uint64_t data, int size) " (0x3d0, 0x%"PRIx64", %d)"
vfio_vga_probe_nvidia_3d0_quirk(const char *name) "Enabled NVIDIA VGA 0x3d0 quirk for device %s"
vfio_probe_nvidia_bar5_window_quirk(const char *name) "Enabled NVIDIA BAR5 window quirk for device %s" vfio_probe_nvidia_bar5_window_quirk(const char *name) "Enabled NVIDIA BAR5 window quirk for device %s"
vfio_probe_nvidia_bar0_88000_quirk(const char *name) "Enabled NVIDIA BAR0 0x88000 quirk for device %s" vfio_probe_nvidia_bar0_88000_quirk(const char *name) "Enabled NVIDIA BAR0 0x88000 quirk for device %s"
vfio_probe_nvidia_bar0_1800_quirk_id(int id) "Nvidia NV%02x" vfio_probe_nvidia_bar0_1800_quirk_id(int id) "Nvidia NV%02x"
@ -1587,6 +1584,10 @@ vfio_pci_reset_pm(const char *name) "%s PCI PM Reset"
vfio_quirk_rom_blacklisted(const char *name, uint16_t vid, uint16_t did) "%s %04x:%04x" vfio_quirk_rom_blacklisted(const char *name, uint16_t vid, uint16_t did) "%s %04x:%04x"
vfio_quirk_ati_3c3_read(const char *name, uint64_t data) "%s 0x%"PRIx64 vfio_quirk_ati_3c3_read(const char *name, uint64_t data) "%s 0x%"PRIx64
vfio_quirk_ati_3c3_probe(const char *name) "%s" vfio_quirk_ati_3c3_probe(const char *name) "%s"
vfio_quirk_nvidia_3d0_state(const char *name, const char *state) "%s %s"
vfio_quirk_nvidia_3d0_read(const char *name, uint8_t offset, unsigned size, uint64_t val) " (%s, @0x%x, len=0x%x) %"PRIx64
vfio_quirk_nvidia_3d0_write(const char *name, uint8_t offset, uint64_t data, unsigned size) "(%s, @0x%x, 0x%"PRIx64", len=0x%x)"
vfio_quirk_nvidia_3d0_probe(const char *name) "%s"
# hw/vfio/vfio-common.c # hw/vfio/vfio-common.c
vfio_region_write(const char *name, int index, uint64_t addr, uint64_t data, unsigned size) " (%s:region%d+0x%"PRIx64", 0x%"PRIx64 ", %d)" vfio_region_write(const char *name, int index, uint64_t addr, uint64_t data, unsigned size) " (%s:region%d+0x%"PRIx64", 0x%"PRIx64 ", %d)"