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hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values

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The SSE-200 and SSE-300 have different PID register values from the
IoTKit for the sysctl register block.  We incorrectly implemented the
SSE-200 with the same PID values as IoTKit.  Fix the SSE-200 bug and
report these register values for SSE-300.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-19-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:45:51 +00:00
parent c5ffe6c8dd
commit 6069bbc904
1 changed files with 19 additions and 2 deletions
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21
hw/misc/iotkit-sysctl.c
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@ -75,12 +75,19 @@ REG32(CID2, 0xff8)
REG32(CID3, 0xffc)
/* PID/CID values */
static const int sysctl_id[] = {
static const int iotkit_sysctl_id[] = {
0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
};
/* Also used by the SSE300 */
static const int sse200_sysctl_id[] = {
0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
0x54, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
};
/*
* Set the initial secure vector table offset address for the core.
* This will take effect when the CPU next resets.
@ -328,7 +335,17 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
}
break;
case A_PID4 ... A_CID3:
r = sysctl_id[(offset - A_PID4) / 4];
switch (s->sse_version) {
case ARMSSE_IOTKIT:
r = iotkit_sysctl_id[(offset - A_PID4) / 4];
break;
case ARMSSE_SSE200:
case ARMSSE_SSE300:
r = sse200_sysctl_id[(offset - A_PID4) / 4];
break;
default:
g_assert_not_reached();
}
break;
case A_SECDBGSET:
case A_SECDBGCLR: