mirror of
https://github.com/xemu-project/xemu.git
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openpic fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@954 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
e1bb04f740
commit
611493d966
135
hw/openpic.c
135
hw/openpic.c
@ -34,7 +34,7 @@
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*/
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#include "vl.h"
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#define DEBUG_OPENPIC
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//#define DEBUG_OPENPIC
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#ifdef DEBUG_OPENPIC
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#define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
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@ -65,7 +65,7 @@
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#define MAX_CPU 2
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#define MAX_IRQ 64
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#define EXT_IRQ 16
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#define EXT_IRQ 48
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#define MAX_DBL 0
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#define MAX_MBX 0
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#define MAX_TMR 4
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@ -139,7 +139,7 @@ typedef struct IRQ_src_t {
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uint32_t ide; /* IRQ destination register */
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int type;
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int last_cpu;
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int waited_acks;
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int pending; /* TRUE if IRQ is pending */
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} IRQ_src_t;
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enum IPVP_bits {
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@ -150,7 +150,7 @@ enum IPVP_bits {
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IPVP_SENSE = 22,
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};
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#define IPVP_PRIORITY_MASK (0x1F << 16)
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#define IPVP_PRIORITY(_ipvpr_) (((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)
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#define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
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#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
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#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
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@ -162,7 +162,7 @@ typedef struct IRQ_dst_t {
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CPUState *env; /* Needed if we did SMP */
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} IRQ_dst_t;
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typedef struct openpic_t {
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struct openpic_t {
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PCIDevice pci_dev;
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/* Global registers */
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uint32_t frep; /* Feature reporting register */
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@ -194,7 +194,7 @@ typedef struct openpic_t {
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uint32_t mbr; /* Mailbox register */
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} mailboxes[MAX_MAILBOXES];
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#endif
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} openpic_t;
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};
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static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
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{
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@ -220,6 +220,8 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
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priority = -1;
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for (i = 0; i < MAX_IRQ; i++) {
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if (IRQ_testbit(q, i)) {
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DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
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i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
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if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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next = i;
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priority = IPVP_PRIORITY(opp->src[i].ipvp);
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@ -233,10 +235,7 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
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static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
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{
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if (q->next == -1) {
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if (q->queue == 0) {
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/* No more IRQ */
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return -1;
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}
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/* XXX: optimize */
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IRQ_check(opp, q);
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}
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@ -269,13 +268,19 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
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}
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}
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void openpic_set_IRQ (openpic_t *opp, int n_IRQ, int level)
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/* update pic state because registers for n_IRQ have changed value */
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static void openpic_update_irq(openpic_t *opp, int n_IRQ)
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{
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IRQ_src_t *src;
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int i;
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src = &opp->src[n_IRQ];
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if (!test_bit(&src->ipvp, IPVP_MASK)) {
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if (!src->pending) {
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/* no irq pending */
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return;
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}
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if (test_bit(&src->ipvp, IPVP_MASK)) {
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/* Interrupt source is disabled */
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return;
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}
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@ -283,43 +288,57 @@ void openpic_set_IRQ (openpic_t *opp, int n_IRQ, int level)
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/* Priority set to zero */
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return;
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}
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if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
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/* IRQ already active */
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return;
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}
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if (src->ide == 0x00000000) {
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/* No target */
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return;
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}
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if (level == 0) {
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if (test_bit(&src->ipvp, IPVP_ACTIVITY) &&
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test_bit(&src->ipvp, IPVP_SENSE)) {
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/* Inactivate a active level-sensitive IRQ */
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reset_bit(&src->ipvp, IPVP_ACTIVITY);
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}
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if (!test_bit(&src->ipvp, IPVP_MODE) ||
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src->ide == (1 << src->last_cpu)) {
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/* Directed delivery mode */
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for (i = 0; i < opp->nb_cpus; i++) {
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if (test_bit(&src->ide, i))
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IRQ_local_pipe(opp, i, n_IRQ);
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}
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} else {
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if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
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/* Interrupt already pending */
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return;
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}
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if (!test_bit(&src->ipvp, IPVP_MODE) ||
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src->ide == (1 << src->last_cpu)) {
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/* Directed delivery mode */
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for (i = 0; i < opp->nb_cpus; i++) {
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if (test_bit(&src->ide, i))
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IRQ_local_pipe(opp, i, n_IRQ);
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}
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} else {
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/* Distributed delivery mode */
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for (i = src->last_cpu; i < src->last_cpu; i++) {
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if (i == MAX_IRQ)
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i = 0;
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if (test_bit(&src->ide, i)) {
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IRQ_local_pipe(opp, i, n_IRQ);
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src->last_cpu = i;
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break;
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}
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}
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}
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/* Distributed delivery mode */
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/* XXX: incorrect code */
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for (i = src->last_cpu; i < src->last_cpu; i++) {
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if (i == MAX_IRQ)
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i = 0;
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if (test_bit(&src->ide, i)) {
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IRQ_local_pipe(opp, i, n_IRQ);
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src->last_cpu = i;
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break;
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}
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}
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}
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}
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void openpic_set_irq(openpic_t *opp, int n_IRQ, int level)
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{
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IRQ_src_t *src;
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src = &opp->src[n_IRQ];
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DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
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n_IRQ, level, src->ipvp);
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if (test_bit(&src->ipvp, IPVP_SENSE)) {
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/* level-sensitive irq */
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src->pending = level;
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if (!level)
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reset_bit(&src->ipvp, IPVP_ACTIVITY);
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} else {
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/* edge-sensitive irq */
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if (level)
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src->pending = 1;
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}
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openpic_update_irq(opp, n_IRQ);
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}
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static void openpic_reset (openpic_t *opp)
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{
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int i;
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@ -389,18 +408,15 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
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switch (reg) {
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case IRQ_IPVP:
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tmp = opp->src[n_IRQ].ipvp & 0x40000000;
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if (tmp == 0) {
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tmp |= val & 0x80000000;
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if ((opp->src[n_IRQ].type & IRQ_EXTERNAL) != 0)
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tmp |= val & 0x40C00000;
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else if ((opp->src[n_IRQ].type & IRQ_TIMER) != 0)
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tmp |= val & 0x00F00000;
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} else {
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tmp |= val & 0x80000000;
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}
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opp->src[n_IRQ].ipvp = tmp | (val & 0x000F00FF);
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DPRINTF("Set IPVP %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ipvp);
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/* NOTE: not fully accurate for special IRQs, but simple and
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sufficient */
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/* ACTIVITY bit is read-only */
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opp->src[n_IRQ].ipvp =
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(opp->src[n_IRQ].ipvp & 0x40000000) |
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(val & 0x800F00FF);
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openpic_update_irq(opp, n_IRQ);
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DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
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n_IRQ, val, opp->src[n_IRQ].ipvp);
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break;
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case IRQ_IDE:
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tmp = val & 0xC0000000;
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@ -736,8 +752,8 @@ static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val)
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case 0x70:
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idx = (addr - 0x40) >> 4;
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write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE, val);
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openpic_set_IRQ(opp, IRQ_IPI0 + idx, 1);
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openpic_set_IRQ(opp, IRQ_IPI0 + idx, 0);
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openpic_set_irq(opp, IRQ_IPI0 + idx, 1);
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openpic_set_irq(opp, IRQ_IPI0 + idx, 0);
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break;
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#endif
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case 0x80: /* PCTP */
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@ -818,8 +834,11 @@ static uint32_t openpic_cpu_read (void *opaque, uint32_t addr)
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}
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IRQ_resetbit(&dst->raised, n_IRQ);
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dst->raised.next = -1;
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if (!test_bit(&src->ipvp, IPVP_SENSE))
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if (!test_bit(&src->ipvp, IPVP_SENSE)) {
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/* edge-sensitive IRQ */
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reset_bit(&src->ipvp, IPVP_ACTIVITY);
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src->pending = 0;
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}
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}
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break;
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case 0xB0: /* PEOI */
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@ -862,7 +881,7 @@ static void openpic_writel (void *opaque,
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openpic_t *opp = opaque;
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addr &= 0x3FFFF;
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DPRINTF("%s: offset %08lx val: %08x\n", __func__, addr, val);
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DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
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if (addr < 0x1100) {
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/* Global registers */
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openpic_gbl_write(opp, addr, val);
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@ -884,7 +903,7 @@ static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
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uint32_t retval;
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addr &= 0x3FFFF;
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DPRINTF("%s: offset %08lx\n", __func__, addr);
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DPRINTF("%s: offset %08x\n", __func__, (int)addr);
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if (addr < 0x1100) {
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/* Global registers */
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retval = openpic_gbl_read(opp, addr);
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