target/xtensa fixes for 2.12:

- add .inc. to non-top level source file names under target/xtensa;
 - fix #include <xtensa-isa.h> in the import_core.sh script;
 - remove stray linux-user/xtensa/syscall.h;
 - fix timers test.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAlq5aMQTHGpjbXZia2Jj
 QGdtYWlsLmNvbQAKCRBR+cyR+D+gRImOEACG+eHvX1kSGetyK/p9OAXDb9QVfASR
 iT7XxW8XRZO+o4bxRLkv3fi5Ye/619Hjj2hWU8Jg4o7weD03kArw/Ft9DyjeJt6p
 EnauA+f6dc9Pwj5PNc0XUtR+wnvijHcnpRoaC+zr2oukIFbIgsgao5YnaovHGuHv
 8R49WUHQFT14KMnuZ2PuICth29UmHd7MFZ2GFmaqggV00S+3CvB2xozLURC2y373
 AlFluHyuB4SNzJad1t0K+pmtxU5NnPd2LTN3l92d35+bNuTBGVp0GMQ8btJVUDr/
 42QRJHHs8AGkm3Q3z3AMzMD5k01+jAySd0eEdQ5v8uCFIYy9HnchLIzyrWxOPwWh
 H+xKivwOdhIc2mP5qdJWQoGemy+Zt9jwfXveu4vjSz4xWGRboxkjW/qbgh8AWT20
 69i4/4uOANDOWiLhGFz7H1VHwJLe9R3G8DxHpEi/Wz0+gBZ7MBk+vrGAlmyzToFm
 U+Zcma1ZJniyAnl/UgVNSZiueC3oLLF8D+VrE9CQJvLOzyoYkPhF2xyjLsDNDe2b
 bwKWwibLNVEBpq1JuENVJ0LEiiv9Ozjc71TuxvvP20NwLsUO65gnGLT+QGD36x5V
 gMGdkUkO/MLRe6whxZ4qB5eWTPU03y7mQyNvbUwzzvG7Zxy4CPlfwzM3x8OwNSiC
 kYKSIBW+Th5UcA==
 =HBTr
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/xtensa/tags/20180326-xtensa' into staging

target/xtensa fixes for 2.12:

- add .inc. to non-top level source file names under target/xtensa;
- fix #include <xtensa-isa.h> in the import_core.sh script;
- remove stray linux-user/xtensa/syscall.h;
- fix timers test.

# gpg: Signature made Mon 26 Mar 2018 22:40:20 BST
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20180326-xtensa:
  target/xtensa: fix timers test
  linux-user/xtensa: remove stray syscall.h
  target/xtensa/import_core.sh: fix #include <xtensa-isa.h>
  target/xtensa: add .inc. to non-top level source file names

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/xtensa/core-dc232b.c

@@ -35,7 +35,7 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_dc232b
-#include "core-dc232b/xtensa-modules.c"
+#include "core-dc232b/xtensa-modules.inc.c"
 
 static XtensaConfig dc232b __attribute__((unused)) = {
     .name = "dc232b",
@@ -43,11 +43,11 @@ static XtensaConfig dc232b __attribute__((unused)) = {
         .num_regs = 120,
         .num_core_regs = 52,
         .reg = {
-#include "core-dc232b/gdb-config.c"
+#include "core-dc232b/gdb-config.inc.c"
         }
     },
     .isa_internal = &xtensa_modules,
-    .clock_freq_khz = 10000,
+    .clock_freq_khz = (NANOSECONDS_PER_SECOND / 64) / 1000,
     DEFAULT_SECTIONS
 };
 

target/xtensa/core-dc233c.c

@@ -36,7 +36,7 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_dc233c
-#include "core-dc233c/xtensa-modules.c"
+#include "core-dc233c/xtensa-modules.inc.c"
 
 static XtensaConfig dc233c __attribute__((unused)) = {
     .name = "dc233c",
@@ -44,7 +44,7 @@ static XtensaConfig dc233c __attribute__((unused)) = {
         .num_regs = 121,
         .num_core_regs = 52,
         .reg = {
-#include "core-dc233c/gdb-config.c"
+#include "core-dc233c/gdb-config.inc.c"
         }
     },
     .isa_internal = &xtensa_modules,

target/xtensa/core-de212.c

@@ -36,13 +36,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_de212
-#include "core-de212/xtensa-modules.c"
+#include "core-de212/xtensa-modules.inc.c"
 
 static XtensaConfig de212 __attribute__((unused)) = {
     .name = "de212",
     .gdb_regmap = {
         .reg = {
-#include "core-de212/gdb-config.c"
+#include "core-de212/gdb-config.inc.c"
         }
     },
     .isa_internal = &xtensa_modules,

target/xtensa/core-fsf.c

@@ -36,7 +36,7 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_fsf
-#include "core-fsf/xtensa-modules.c"
+#include "core-fsf/xtensa-modules.inc.c"
 
 static XtensaConfig fsf __attribute__((unused)) = {
     .name = "fsf",

target/xtensa/core-sample_controller.c

@@ -36,13 +36,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_sample_controller
-#include "core-sample_controller/xtensa-modules.c"
+#include "core-sample_controller/xtensa-modules.inc.c"
 
 static XtensaConfig sample_controller __attribute__((unused)) = {
     .name = "sample_controller",
     .gdb_regmap = {
         .reg = {
-#include "core-sample_controller/gdb-config.c"
+#include "core-sample_controller/gdb-config.inc.c"
         }
     },
     .isa_internal = &xtensa_modules,

target/xtensa/import_core.sh

@@ -22,7 +22,7 @@ mkdir -p "$TARGET"
 tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \
     --xform='s/core/core-isa/' config/core.h
 tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
-    sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c
+    sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c
 #
 # Fix up known issues in the xtensa-modules.c
 #
@@ -33,7 +33,8 @@ tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \
         -e '/^uint32 \*bypass_entry(int i)/,/}/d' \
         -e '/^#include "ansidecl.h"/d' \
         -e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^  return 0;$/  return XTENSA_UNDEFINED;/' \
-    > "$TARGET"/xtensa-modules.c
+        -e 's/#include <xtensa-isa.h>/#include "xtensa-isa.h"/' \
+    > "$TARGET"/xtensa-modules.inc.c
 
 cat <<EOF > "${TARGET}.c"
 #include "qemu/osdep.h"
@@ -47,13 +48,13 @@ cat <<EOF > "${TARGET}.c"
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_$NAME
-#include "core-$NAME/xtensa-modules.c"
+#include "core-$NAME/xtensa-modules.inc.c"
 
 static XtensaConfig $NAME __attribute__((unused)) = {
     .name = "$NAME",
     .gdb_regmap = {
         .reg = {
-#include "core-$NAME/gdb-config.c"
+#include "core-$NAME/gdb-config.inc.c"
         }
     },
     .isa_internal = &xtensa_modules,

tests/tcg/xtensa/Makefile

@@ -5,7 +5,7 @@ CROSS=xtensa-$(CORE)-elf-
 
 ifndef XT
 SIM = ../../../xtensa-softmmu/qemu-system-xtensa
-SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting -icount 7 $(EXTFLAGS) -kernel
+SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel
 SIMDEBUG = -s -S
 else
 SIM = xt-run