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hw/char: RX62N serial communication interface (SCI)
This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-17-ysato@users.sourceforge.jp> [PMD: Filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Yoshinori Sato
Philippe Mathieu-Daudé
parent
c7f37bafde
commit
645194c7aa
@ -1971,9 +1971,11 @@ Renesas peripherals
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M: Yoshinori Sato <ysato@users.sourceforge.jp>
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R: Magnus Damm <magnus.damm@gmail.com>
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S: Maintained
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F: hw/char/renesas_sci.c
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F: hw/char/sh_serial.c
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F: hw/timer/renesas_*.c
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F: hw/timer/sh_timer.c
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F: include/hw/char/renesas_sci.h
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F: include/hw/sh4/sh.h
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F: include/hw/timer/renesas_*.h
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@ -46,3 +46,6 @@ config SCLPCONSOLE
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config TERMINAL3270
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bool
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config RENESAS_SCI
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bool
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@ -21,6 +21,7 @@ common-obj-$(CONFIG_SH4) += sh_serial.o
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common-obj-$(CONFIG_DIGIC) += digic-uart.o
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common-obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
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common-obj-$(CONFIG_RASPI) += bcm2835_aux.o
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common-obj-$(CONFIG_RENESAS_SCI) += renesas_sci.o
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common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
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350
hw/char/renesas_sci.c
Normal file
350
hw/char/renesas_sci.c
Normal file
@ -0,0 +1,350 @@
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/*
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* Renesas Serial Communication Interface
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*
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* Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
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* (Rev.1.40 R01UH0033EJ0140)
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/qdev-properties.h"
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#include "hw/char/renesas_sci.h"
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#include "migration/vmstate.h"
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/* SCI register map */
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REG8(SMR, 0)
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FIELD(SMR, CKS, 0, 2)
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FIELD(SMR, MP, 2, 1)
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FIELD(SMR, STOP, 3, 1)
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FIELD(SMR, PM, 4, 1)
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FIELD(SMR, PE, 5, 1)
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FIELD(SMR, CHR, 6, 1)
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FIELD(SMR, CM, 7, 1)
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REG8(BRR, 1)
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REG8(SCR, 2)
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FIELD(SCR, CKE, 0, 2)
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FIELD(SCR, TEIE, 2, 1)
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FIELD(SCR, MPIE, 3, 1)
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FIELD(SCR, RE, 4, 1)
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FIELD(SCR, TE, 5, 1)
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FIELD(SCR, RIE, 6, 1)
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FIELD(SCR, TIE, 7, 1)
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REG8(TDR, 3)
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REG8(SSR, 4)
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FIELD(SSR, MPBT, 0, 1)
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FIELD(SSR, MPB, 1, 1)
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FIELD(SSR, TEND, 2, 1)
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FIELD(SSR, ERR, 3, 3)
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FIELD(SSR, PER, 3, 1)
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FIELD(SSR, FER, 4, 1)
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FIELD(SSR, ORER, 5, 1)
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FIELD(SSR, RDRF, 6, 1)
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FIELD(SSR, TDRE, 7, 1)
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REG8(RDR, 5)
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REG8(SCMR, 6)
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FIELD(SCMR, SMIF, 0, 1)
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FIELD(SCMR, SINV, 2, 1)
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FIELD(SCMR, SDIR, 3, 1)
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FIELD(SCMR, BCP2, 7, 1)
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REG8(SEMR, 7)
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FIELD(SEMR, ACS0, 0, 1)
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FIELD(SEMR, ABCS, 4, 1)
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static int can_receive(void *opaque)
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{
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RSCIState *sci = RSCI(opaque);
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if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
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return 0;
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} else {
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return FIELD_EX8(sci->scr, SCR, RE);
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}
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}
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static void receive(void *opaque, const uint8_t *buf, int size)
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{
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RSCIState *sci = RSCI(opaque);
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sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime;
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if (FIELD_EX8(sci->ssr, SSR, RDRF) || size > 1) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, ORER, 1);
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if (FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_set_irq(sci->irq[ERI], 1);
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}
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} else {
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sci->rdr = buf[0];
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sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 1);
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if (FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_irq_pulse(sci->irq[RXI]);
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}
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}
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}
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static void send_byte(RSCIState *sci)
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{
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if (qemu_chr_fe_backend_connected(&sci->chr)) {
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qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1);
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}
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timer_mod(&sci->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 0);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
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qemu_set_irq(sci->irq[TEI], 0);
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if (FIELD_EX8(sci->scr, SCR, TIE)) {
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qemu_irq_pulse(sci->irq[TXI]);
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}
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}
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static void txend(void *opaque)
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{
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RSCIState *sci = RSCI(opaque);
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if (!FIELD_EX8(sci->ssr, SSR, TDRE)) {
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send_byte(sci);
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} else {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
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if (FIELD_EX8(sci->scr, SCR, TEIE)) {
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qemu_set_irq(sci->irq[TEI], 1);
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}
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}
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}
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static void update_trtime(RSCIState *sci)
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{
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/* char per bits */
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sci->trtime = 8 - FIELD_EX8(sci->smr, SMR, CHR);
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sci->trtime += FIELD_EX8(sci->smr, SMR, PE);
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sci->trtime += FIELD_EX8(sci->smr, SMR, STOP) + 1;
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/* x bit transmit time (32 * divrate * brr) / base freq */
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sci->trtime *= 32 * sci->brr;
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sci->trtime *= 1 << (2 * FIELD_EX8(sci->smr, SMR, CKS));
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sci->trtime *= NANOSECONDS_PER_SECOND;
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sci->trtime /= sci->input_freq;
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}
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static bool sci_is_tr_enabled(RSCIState *sci)
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{
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return FIELD_EX8(sci->scr, SCR, TE) || FIELD_EX8(sci->scr, SCR, RE);
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}
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static void sci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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{
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RSCIState *sci = RSCI(opaque);
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switch (offset) {
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case A_SMR:
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if (!sci_is_tr_enabled(sci)) {
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sci->smr = val;
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update_trtime(sci);
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}
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break;
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case A_BRR:
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if (!sci_is_tr_enabled(sci)) {
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sci->brr = val;
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update_trtime(sci);
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}
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break;
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case A_SCR:
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sci->scr = val;
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if (FIELD_EX8(sci->scr, SCR, TE)) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 1);
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TEND, 1);
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if (FIELD_EX8(sci->scr, SCR, TIE)) {
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qemu_irq_pulse(sci->irq[TXI]);
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}
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}
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if (!FIELD_EX8(sci->scr, SCR, TEIE)) {
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qemu_set_irq(sci->irq[TEI], 0);
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}
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if (!FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_set_irq(sci->irq[ERI], 0);
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}
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break;
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case A_TDR:
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sci->tdr = val;
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if (FIELD_EX8(sci->ssr, SSR, TEND)) {
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send_byte(sci);
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} else {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, TDRE, 0);
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}
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break;
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case A_SSR:
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sci->ssr = FIELD_DP8(sci->ssr, SSR, MPBT,
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FIELD_EX8(val, SSR, MPBT));
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sci->ssr = FIELD_DP8(sci->ssr, SSR, ERR,
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FIELD_EX8(val, SSR, ERR) & 0x07);
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if (FIELD_EX8(sci->read_ssr, SSR, ERR) &&
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FIELD_EX8(sci->ssr, SSR, ERR) == 0) {
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qemu_set_irq(sci->irq[ERI], 0);
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}
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break;
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case A_RDR:
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qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n");
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break;
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case A_SCMR:
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sci->scmr = val; break;
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case A_SEMR: /* SEMR */
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sci->semr = val; break;
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default:
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qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX " "
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"not implemented\n",
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offset);
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}
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}
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static uint64_t sci_read(void *opaque, hwaddr offset, unsigned size)
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{
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RSCIState *sci = RSCI(opaque);
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switch (offset) {
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case A_SMR:
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return sci->smr;
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case A_BRR:
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return sci->brr;
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case A_SCR:
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return sci->scr;
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case A_TDR:
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return sci->tdr;
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case A_SSR:
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sci->read_ssr = sci->ssr;
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return sci->ssr;
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case A_RDR:
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sci->ssr = FIELD_DP8(sci->ssr, SSR, RDRF, 0);
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return sci->rdr;
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case A_SCMR:
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return sci->scmr;
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case A_SEMR:
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return sci->semr;
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default:
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qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
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" not implemented.\n", offset);
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}
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return UINT64_MAX;
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}
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static const MemoryRegionOps sci_ops = {
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.write = sci_write,
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.read = sci_read,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.max_access_size = 1,
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.valid.max_access_size = 1,
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};
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static void rsci_reset(DeviceState *dev)
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{
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RSCIState *sci = RSCI(dev);
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sci->smr = sci->scr = 0x00;
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sci->brr = 0xff;
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sci->tdr = 0xff;
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sci->rdr = 0x00;
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sci->ssr = 0x84;
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sci->scmr = 0x00;
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sci->semr = 0x00;
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sci->rx_next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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}
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static void sci_event(void *opaque, QEMUChrEvent event)
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{
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RSCIState *sci = RSCI(opaque);
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if (event == CHR_EVENT_BREAK) {
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sci->ssr = FIELD_DP8(sci->ssr, SSR, FER, 1);
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if (FIELD_EX8(sci->scr, SCR, RIE)) {
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qemu_set_irq(sci->irq[ERI], 1);
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}
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}
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}
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static void rsci_realize(DeviceState *dev, Error **errp)
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{
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RSCIState *sci = RSCI(dev);
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if (sci->input_freq == 0) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"renesas_sci: input-freq property must be set.");
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return;
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}
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qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive,
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sci_event, NULL, sci, NULL, true);
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}
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static void rsci_init(Object *obj)
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{
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SysBusDevice *d = SYS_BUS_DEVICE(obj);
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RSCIState *sci = RSCI(obj);
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int i;
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memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops,
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sci, "renesas-sci", 0x8);
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sysbus_init_mmio(d, &sci->memory);
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for (i = 0; i < SCI_NR_IRQ; i++) {
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sysbus_init_irq(d, &sci->irq[i]);
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}
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timer_init_ns(&sci->timer, QEMU_CLOCK_VIRTUAL, txend, sci);
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}
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static const VMStateDescription vmstate_rsci = {
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.name = "renesas-sci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT64(trtime, RSCIState),
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VMSTATE_INT64(rx_next, RSCIState),
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VMSTATE_UINT8(smr, RSCIState),
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VMSTATE_UINT8(brr, RSCIState),
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VMSTATE_UINT8(scr, RSCIState),
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VMSTATE_UINT8(tdr, RSCIState),
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VMSTATE_UINT8(ssr, RSCIState),
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VMSTATE_UINT8(rdr, RSCIState),
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VMSTATE_UINT8(scmr, RSCIState),
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VMSTATE_UINT8(semr, RSCIState),
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VMSTATE_UINT8(read_ssr, RSCIState),
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VMSTATE_TIMER(timer, RSCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property rsci_properties[] = {
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DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0),
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DEFINE_PROP_CHR("chardev", RSCIState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void rsci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = rsci_realize;
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dc->vmsd = &vmstate_rsci;
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dc->reset = rsci_reset;
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device_class_set_props(dc, rsci_properties);
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}
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static const TypeInfo rsci_info = {
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.name = TYPE_RENESAS_SCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RSCIState),
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.instance_init = rsci_init,
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.class_init = rsci_class_init,
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};
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static void rsci_register_types(void)
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{
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type_register_static(&rsci_info);
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}
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type_init(rsci_register_types)
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51
include/hw/char/renesas_sci.h
Normal file
51
include/hw/char/renesas_sci.h
Normal file
@ -0,0 +1,51 @@
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/*
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* Renesas Serial Communication Interface
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*
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* Copyright (c) 2018 Yoshinori Sato
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_CHAR_RENESAS_SCI_H
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#define HW_CHAR_RENESAS_SCI_H
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#include "chardev/char-fe.h"
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#include "hw/sysbus.h"
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#define TYPE_RENESAS_SCI "renesas-sci"
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#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI)
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enum {
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ERI = 0,
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RXI = 1,
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TXI = 2,
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TEI = 3,
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SCI_NR_IRQ = 4
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};
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typedef struct {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion memory;
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QEMUTimer timer;
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CharBackend chr;
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qemu_irq irq[SCI_NR_IRQ];
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uint8_t smr;
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uint8_t brr;
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uint8_t scr;
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uint8_t tdr;
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uint8_t ssr;
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uint8_t rdr;
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uint8_t scmr;
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uint8_t semr;
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uint8_t read_ssr;
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int64_t trtime;
|
||||
int64_t rx_next;
|
||||
uint64_t input_freq;
|
||||
} RSCIState;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user