xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-30 23:10:38 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target/ppc: 405: Rename MSR_POW to MSR_WE

Browse Source 
Bit 13 is the Wait State Enable bit. Give it its proper name.

As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.

Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Fabiano Rosas 2022-01-28 13:15:03 +01:00 committed by Cédric Le Goater
parent 47822486f5
commit 645d843ca5
2 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/ppc/cpu.h
View File

@ -327,6 +327,7 @@ typedef enum {
#define MSR_S 22 /* Secure state */ #define MSR_S 22 /* Secure state */
#define MSR_KEY 19 /* key bit on 603e */ #define MSR_KEY 19 /* key bit on 603e */
#define MSR_POW 18 /* Power management */ #define MSR_POW 18 /* Power management */
#define MSR_WE 18 /* Wait State Enable on 405 */
#define MSR_TGPR 17 /* TGPR usage on 602/603 x */ #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
#define MSR_ILE 16 /* Interrupt little-endian mode */ #define MSR_ILE 16 /* Interrupt little-endian mode */

2
target/ppc/cpu_init.c
View File

@ -2535,7 +2535,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
pcc->msr_mask = (1ull << MSR_POW) | pcc->msr_mask = (1ull << MSR_WE) |
(1ull << MSR_CE) | (1ull << MSR_CE) |
(1ull << MSR_EE) | (1ull << MSR_EE) |
(1ull << MSR_PR) | (1ull << MSR_PR) |