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tcg/ppc: Update vector support for v2.07 Altivec
These new instructions are conditional only on MSR.VEC and are thus part of the Altivec instruction set, and not VSX. This includes lots of double-word arithmetic and a few extra logical operations. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
47c906ae6f
commit
64ff1c6d21
@ -61,6 +61,7 @@ typedef enum {
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typedef enum {
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tcg_isa_base,
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tcg_isa_2_06,
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tcg_isa_2_07,
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tcg_isa_3_00,
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} TCGPowerISA;
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@ -69,6 +70,7 @@ extern bool have_altivec;
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extern bool have_vsx;
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#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
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#define have_isa_2_07 (have_isa >= tcg_isa_2_07)
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#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
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/* optional instructions automatically implemented */
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@ -155,7 +157,7 @@ extern bool have_vsx;
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#define TCG_TARGET_HAS_v256 0
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec 0
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#define TCG_TARGET_HAS_orc_vec have_isa_2_07
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec 0
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#define TCG_TARGET_HAS_abs_vec 0
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@ -484,6 +484,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define VADDSWS VX4(896)
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#define VADDUWS VX4(640)
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#define VADDUWM VX4(128)
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#define VADDUDM VX4(192) /* v2.07 */
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#define VSUBSBS VX4(1792)
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#define VSUBUBS VX4(1536)
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@ -494,47 +495,62 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define VSUBSWS VX4(1920)
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#define VSUBUWS VX4(1664)
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#define VSUBUWM VX4(1152)
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#define VSUBUDM VX4(1216) /* v2.07 */
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#define VMAXSB VX4(258)
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#define VMAXSH VX4(322)
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#define VMAXSW VX4(386)
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#define VMAXSD VX4(450) /* v2.07 */
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#define VMAXUB VX4(2)
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#define VMAXUH VX4(66)
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#define VMAXUW VX4(130)
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#define VMAXUD VX4(194) /* v2.07 */
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#define VMINSB VX4(770)
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#define VMINSH VX4(834)
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#define VMINSW VX4(898)
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#define VMINSD VX4(962) /* v2.07 */
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#define VMINUB VX4(514)
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#define VMINUH VX4(578)
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#define VMINUW VX4(642)
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#define VMINUD VX4(706) /* v2.07 */
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#define VCMPEQUB VX4(6)
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#define VCMPEQUH VX4(70)
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#define VCMPEQUW VX4(134)
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#define VCMPEQUD VX4(199) /* v2.07 */
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#define VCMPGTSB VX4(774)
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#define VCMPGTSH VX4(838)
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#define VCMPGTSW VX4(902)
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#define VCMPGTSD VX4(967) /* v2.07 */
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#define VCMPGTUB VX4(518)
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#define VCMPGTUH VX4(582)
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#define VCMPGTUW VX4(646)
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#define VCMPGTUD VX4(711) /* v2.07 */
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#define VSLB VX4(260)
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#define VSLH VX4(324)
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#define VSLW VX4(388)
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#define VSLD VX4(1476) /* v2.07 */
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#define VSRB VX4(516)
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#define VSRH VX4(580)
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#define VSRW VX4(644)
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#define VSRD VX4(1732) /* v2.07 */
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#define VSRAB VX4(772)
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#define VSRAH VX4(836)
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#define VSRAW VX4(900)
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#define VSRAD VX4(964) /* v2.07 */
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#define VRLB VX4(4)
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#define VRLH VX4(68)
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#define VRLW VX4(132)
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#define VRLD VX4(196) /* v2.07 */
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#define VMULEUB VX4(520)
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#define VMULEUH VX4(584)
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#define VMULEUW VX4(648) /* v2.07 */
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#define VMULOUB VX4(8)
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#define VMULOUH VX4(72)
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#define VMULOUW VX4(136) /* v2.07 */
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#define VMULUWM VX4(137) /* v2.07 */
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#define VMSUMUHM VX4(38)
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#define VMRGHB VX4(12)
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@ -552,6 +568,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define VNOR VX4(1284)
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#define VOR VX4(1156)
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#define VXOR VX4(1220)
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#define VEQV VX4(1668) /* v2.07 */
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#define VNAND VX4(1412) /* v2.07 */
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#define VORC VX4(1348) /* v2.07 */
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#define VSPLTB VX4(524)
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#define VSPLTH VX4(588)
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@ -2904,26 +2923,37 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_andc_vec:
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case INDEX_op_not_vec:
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return 1;
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case INDEX_op_orc_vec:
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return have_isa_2_07;
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case INDEX_op_add_vec:
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case INDEX_op_sub_vec:
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case INDEX_op_smax_vec:
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case INDEX_op_smin_vec:
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case INDEX_op_umax_vec:
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case INDEX_op_umin_vec:
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case INDEX_op_shlv_vec:
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case INDEX_op_shrv_vec:
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case INDEX_op_sarv_vec:
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return vece <= MO_32 || have_isa_2_07;
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case INDEX_op_ssadd_vec:
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case INDEX_op_sssub_vec:
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case INDEX_op_usadd_vec:
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case INDEX_op_ussub_vec:
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case INDEX_op_shlv_vec:
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case INDEX_op_shrv_vec:
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case INDEX_op_sarv_vec:
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return vece <= MO_32;
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case INDEX_op_cmp_vec:
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case INDEX_op_mul_vec:
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case INDEX_op_shli_vec:
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case INDEX_op_shri_vec:
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case INDEX_op_sari_vec:
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return vece <= MO_32 ? -1 : 0;
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return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
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case INDEX_op_mul_vec:
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switch (vece) {
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case MO_8:
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case MO_16:
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return -1;
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case MO_32:
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return have_isa_2_07 ? 1 : -1;
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}
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return 0;
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case INDEX_op_bitsel_vec:
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return have_vsx;
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default:
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@ -3027,28 +3057,28 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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const TCGArg *args, const int *const_args)
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{
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static const uint32_t
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add_op[4] = { VADDUBM, VADDUHM, VADDUWM, 0 },
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sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, 0 },
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eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
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gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
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gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
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add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
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sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
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eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
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gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
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gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
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ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
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usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
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sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
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ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
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umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
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smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
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umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
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smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
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shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
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shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
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sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 },
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umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
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smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
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umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
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smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
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shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
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shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
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sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
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mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
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mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
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muleu_op[4] = { VMULEUB, VMULEUH, 0, 0 },
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mulou_op[4] = { VMULOUB, VMULOUH, 0, 0 },
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muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
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mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
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pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
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rotl_op[4] = { VRLB, VRLH, VRLW, 0 };
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rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
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TCGType type = vecl + TCG_TYPE_V64;
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TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
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@ -3071,6 +3101,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_sub_vec:
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insn = sub_op[vece];
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break;
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case INDEX_op_mul_vec:
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tcg_debug_assert(vece == MO_32 && have_isa_2_07);
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insn = VMULUWM;
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break;
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case INDEX_op_ssadd_vec:
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insn = ssadd_op[vece];
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break;
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@ -3120,6 +3154,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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insn = VNOR;
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a2 = a1;
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break;
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case INDEX_op_orc_vec:
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insn = VORC;
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break;
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case INDEX_op_cmp_vec:
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switch (args[3]) {
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@ -3200,7 +3237,7 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
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{
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bool need_swap = false, need_inv = false;
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tcg_debug_assert(vece <= MO_32);
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tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
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switch (cond) {
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case TCG_COND_EQ:
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@ -3264,6 +3301,7 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
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break;
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case MO_32:
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tcg_debug_assert(!have_isa_2_07);
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t3 = tcg_temp_new_vec(type);
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t4 = tcg_temp_new_vec(type);
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tcg_gen_dupi_vec(MO_8, t4, -16);
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@ -3554,6 +3592,11 @@ static void tcg_target_init(TCGContext *s)
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if (hwcap & PPC_FEATURE_ARCH_2_06) {
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have_isa = tcg_isa_2_06;
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}
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#ifdef PPC_FEATURE2_ARCH_2_07
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if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
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have_isa = tcg_isa_2_07;
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}
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#endif
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#ifdef PPC_FEATURE2_ARCH_3_00
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if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
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have_isa = tcg_isa_3_00;
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