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target/openrisc: Interrupt handling fixes

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When running SMP systems we sometimes were seeing lockups where
IPI interrupts were being raised by never handled.

This looks to be caused by 2 issues in the openrisc interrupt handling
logic.

 1. After clearing an interrupt the openrisc_cpu_set_irq handler will
    always clear PICSR.  This is not correct as masked interrupts
    should still be visible in PICSR.
 2. After setting PICMR (mask register) and exposed interrupts should
    cause an interrupt to be raised.  This was not being done so add it.

This patch fixes both issues.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2022-06-24 05:44:56 +09:00
parent 6a0fc96ad2
commit 66564c31e4
2 changed files with 7 additions and 1 deletions
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1
target/openrisc/cpu.c
View File

@ -98,7 +98,6 @@ static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
cpu->env.picsr = 0;
}
}
#endif

7
target/openrisc/sys_helper.c
View File

@ -139,6 +139,13 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(9, 0): /* PICMR */
env->picmr = rb;
qemu_mutex_lock_iothread();
if (env->picsr & env->picmr) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
qemu_mutex_unlock_iothread();
break;
case TO_SPR(9, 2): /* PICSR */
env->picsr &= ~rb;