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kvm: x86: Add user space part for in-kernel APIC
This introduces the alternative APIC device which makes use of KVM's in-kernel device model. External NMI injection via LINT1 is emulated by checking the current state of the in-kernel APIC, only injecting a NMI into the VCPU if LINT1 is unmasked and configured to DM_NMI. MSI is not yet supported, so we disable this when the in-kernel model is in use. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
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@ -233,7 +233,7 @@ obj-i386-y += vmport.o
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obj-i386-y += pci-hotplug.o smbios.o wdt_ib700.o
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obj-i386-y += debugcon.o multiboot.o
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obj-i386-y += pc_piix.o
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obj-i386-$(CONFIG_KVM) += kvm/clock.o
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obj-i386-$(CONFIG_KVM) += kvm/clock.o kvm/apic.o
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obj-i386-$(CONFIG_SPICE) += qxl.o qxl-logger.o qxl-render.o
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# shared objects
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138
hw/kvm/apic.c
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138
hw/kvm/apic.c
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@ -0,0 +1,138 @@
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/*
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* KVM in-kernel APIC support
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*
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* Copyright (c) 2011 Siemens AG
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL version 2.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw/apic_internal.h"
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#include "kvm.h"
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static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
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int reg_id, uint32_t val)
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{
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*((uint32_t *)(kapic->regs + (reg_id << 4))) = val;
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}
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static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic,
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int reg_id)
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{
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return *((uint32_t *)(kapic->regs + (reg_id << 4)));
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}
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void kvm_put_apic_state(DeviceState *d, struct kvm_lapic_state *kapic)
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
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int i;
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memset(kapic, 0, sizeof(kapic));
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kvm_apic_set_reg(kapic, 0x2, s->id << 24);
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kvm_apic_set_reg(kapic, 0x8, s->tpr);
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kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24);
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kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
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kvm_apic_set_reg(kapic, 0xf, s->spurious_vec);
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for (i = 0; i < 8; i++) {
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kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]);
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kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]);
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kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]);
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}
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kvm_apic_set_reg(kapic, 0x28, s->esr);
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kvm_apic_set_reg(kapic, 0x30, s->icr[0]);
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kvm_apic_set_reg(kapic, 0x31, s->icr[1]);
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for (i = 0; i < APIC_LVT_NB; i++) {
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kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]);
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}
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kvm_apic_set_reg(kapic, 0x38, s->initial_count);
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kvm_apic_set_reg(kapic, 0x3e, s->divide_conf);
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}
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void kvm_get_apic_state(DeviceState *d, struct kvm_lapic_state *kapic)
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
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int i, v;
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s->id = kvm_apic_get_reg(kapic, 0x2) >> 24;
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s->tpr = kvm_apic_get_reg(kapic, 0x8);
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s->arb_id = kvm_apic_get_reg(kapic, 0x9);
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s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24;
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s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28;
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s->spurious_vec = kvm_apic_get_reg(kapic, 0xf);
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for (i = 0; i < 8; i++) {
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s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i);
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s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i);
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s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i);
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}
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s->esr = kvm_apic_get_reg(kapic, 0x28);
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s->icr[0] = kvm_apic_get_reg(kapic, 0x30);
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s->icr[1] = kvm_apic_get_reg(kapic, 0x31);
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for (i = 0; i < APIC_LVT_NB; i++) {
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s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i);
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}
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s->initial_count = kvm_apic_get_reg(kapic, 0x38);
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s->divide_conf = kvm_apic_get_reg(kapic, 0x3e);
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v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
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s->count_shift = (v + 1) & 7;
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s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
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apic_next_timer(s, s->initial_count_load_time);
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}
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static void kvm_apic_set_base(APICCommonState *s, uint64_t val)
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{
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s->apicbase = val;
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}
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static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val)
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{
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s->tpr = (val & 0x0f) << 4;
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}
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static void do_inject_external_nmi(void *data)
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{
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APICCommonState *s = data;
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CPUState *env = s->cpu_env;
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uint32_t lvt;
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int ret;
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cpu_synchronize_state(env);
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lvt = s->lvt[APIC_LVT_LINT1];
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if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
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ret = kvm_vcpu_ioctl(env, KVM_NMI);
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if (ret < 0) {
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fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
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strerror(-ret));
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}
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}
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}
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static void kvm_apic_external_nmi(APICCommonState *s)
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{
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run_on_cpu(s->cpu_env, do_inject_external_nmi, s);
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}
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static void kvm_apic_init(APICCommonState *s)
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{
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memory_region_init_reservation(&s->io_memory, "kvm-apic-msi",
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MSI_SPACE_SIZE);
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}
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static APICCommonInfo kvm_apic_info = {
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.busdev.qdev.name = "kvm-apic",
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.init = kvm_apic_init,
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.set_base = kvm_apic_set_base,
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.set_tpr = kvm_apic_set_tpr,
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.external_nmi = kvm_apic_external_nmi,
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};
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static void kvm_apic_register_device(void)
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{
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apic_qdev_register(&kvm_apic_info);
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}
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device_init(kvm_apic_register_device)
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15
hw/pc.c
15
hw/pc.c
@ -879,25 +879,30 @@ DeviceState *cpu_get_current_apic(void)
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static DeviceState *apic_init(void *env, uint8_t apic_id)
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{
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DeviceState *dev;
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SysBusDevice *d;
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static int apic_mapped;
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dev = qdev_create(NULL, "apic");
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if (kvm_enabled() && kvm_irqchip_in_kernel()) {
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dev = qdev_create(NULL, "kvm-apic");
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} else {
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dev = qdev_create(NULL, "apic");
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}
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qdev_prop_set_uint8(dev, "id", apic_id);
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qdev_prop_set_ptr(dev, "cpu_env", env);
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qdev_init_nofail(dev);
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d = sysbus_from_qdev(dev);
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/* XXX: mapping more APICs at the same memory location */
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if (apic_mapped == 0) {
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/* NOTE: the APIC is directly connected to the CPU - it is not
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on the global memory bus. */
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/* XXX: what if the base changes? */
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sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
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apic_mapped = 1;
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}
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msi_supported = true;
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/* KVM does not support MSI yet. */
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if (!kvm_enabled() || !kvm_irqchip_in_kernel()) {
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msi_supported = true;
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}
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return dev;
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}
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4
kvm.h
4
kvm.h
@ -31,6 +31,7 @@ extern int kvm_allowed;
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#endif
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struct kvm_run;
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struct kvm_lapic_state;
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typedef struct KVMCapabilityInfo {
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const char *name;
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@ -134,6 +135,9 @@ int kvm_irqchip_set_irq(KVMState *s, int irq, int level);
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void kvm_irqchip_add_route(KVMState *s, int gsi, int irqchip, int pin);
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int kvm_irqchip_commit_routes(KVMState *s);
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void kvm_put_apic_state(DeviceState *d, struct kvm_lapic_state *kapic);
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void kvm_get_apic_state(DeviceState *d, struct kvm_lapic_state *kapic);
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struct kvm_guest_debug;
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struct kvm_debug_exit_arch;
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@ -1337,6 +1337,36 @@ static int kvm_get_mp_state(CPUState *env)
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return 0;
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}
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static int kvm_get_apic(CPUState *env)
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{
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DeviceState *apic = env->apic_state;
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struct kvm_lapic_state kapic;
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int ret;
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if (apic && kvm_enabled() && kvm_irqchip_in_kernel()) {
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ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
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if (ret < 0) {
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return ret;
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}
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kvm_get_apic_state(apic, &kapic);
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}
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return 0;
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}
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static int kvm_put_apic(CPUState *env)
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{
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DeviceState *apic = env->apic_state;
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struct kvm_lapic_state kapic;
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if (apic && kvm_enabled() && kvm_irqchip_in_kernel()) {
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kvm_put_apic_state(apic, &kapic);
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return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
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}
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return 0;
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}
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static int kvm_put_vcpu_events(CPUState *env, int level)
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{
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struct kvm_vcpu_events events;
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@ -1510,6 +1540,10 @@ int kvm_arch_put_registers(CPUState *env, int level)
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if (ret < 0) {
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return ret;
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}
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ret = kvm_put_apic(env);
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if (ret < 0) {
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return ret;
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}
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}
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ret = kvm_put_vcpu_events(env, level);
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if (ret < 0) {
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@ -1557,6 +1591,10 @@ int kvm_arch_get_registers(CPUState *env)
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if (ret < 0) {
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return ret;
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}
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ret = kvm_get_apic(env);
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if (ret < 0) {
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return ret;
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}
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ret = kvm_get_vcpu_events(env);
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if (ret < 0) {
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return ret;
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