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tests/tcg/xtensa: add DFP0 arithmetic tests
Add test for basic double precision opcode properties. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Max Filippov
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162
tests/tcg/xtensa/test_dfp0_arith.S
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162
tests/tcg/xtensa/test_dfp0_arith.S
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#include "macros.inc"
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#include "fpu.h"
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test_suite fp0_arith
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#if XCHAL_HAVE_DFP
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.macro movfp fr, v
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movi a2, ((\v) >> 32) & 0xffffffff
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movi a3, ((\v) & 0xffffffff)
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wfrd \fr, a2, a3
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.endm
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.macro check_res fr, r, sr
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rfrd a2, \fr
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dump a2
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movi a3, ((\r) >> 32) & 0xffffffff
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assert eq, a2, a3
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rfr a2, \fr
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dump a2
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movi a3, ((\r) & 0xffffffff)
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assert eq, a2, a3
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rur a2, fsr
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movi a3, \sr
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assert eq, a2, a3
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.endm
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test add_d
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movi a2, 1
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wsr a2, cpenable
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/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
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test_op2 add.d, f6, f7, f8, F64_MAX, F64_MAX, \
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F64_PINF, F64_MAX, F64_PINF, F64_MAX, \
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FSR_OI, FSR_OI, FSR_OI, FSR_OI
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test_end
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test add_d_inf
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/* 1 + +inf = +inf */
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test_op2 add.d, f6, f7, f8, F64_1, F64_PINF, \
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F64_PINF, F64_PINF, F64_PINF, F64_PINF, \
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FSR__, FSR__, FSR__, FSR__
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/* +inf + -inf = default NaN */
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test_op2 add.d, f0, f1, f2, F64_PINF, F64_NINF, \
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F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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test add_d_nan_dfpu
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/* 1 + QNaN = QNaN */
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test_op2 add.d, f9, f10, f11, F64_1, F64_QNAN(1), \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* 1 + SNaN = QNaN */
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test_op2 add.d, f12, f13, f14, F64_1, F64_SNAN(1), \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* SNaN1 + SNaN2 = QNaN2 */
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test_op2 add.d, f15, f0, f1, F64_SNAN(1), F64_SNAN(2), \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* QNaN1 + SNaN2 = QNaN2 */
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test_op2 add.d, f5, f6, f7, F64_QNAN(1), F64_SNAN(2), \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* SNaN1 + QNaN2 = QNaN2 */
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test_op2 add.d, f8, f9, f10, F64_SNAN(1), F64_QNAN(2), \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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test sub_d
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/* norm - norm = denorm */
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test_op2 sub.d, f6, f7, f8, F64_MIN_NORM | 1, F64_MIN_NORM, \
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0x00000001, 0x00000001, 0x00000001, 0x00000001, \
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FSR__, FSR__, FSR__, FSR__
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test_end
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test mul_d
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test_op2 mul.d, f0, f1, f2, F64_1 | 1, F64_1 | 1, \
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F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \
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FSR_I, FSR_I, FSR_I, FSR_I
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/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
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test_op2 mul.d, f6, f7, f8, F64_MAX_2, F64_MAX_2, \
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F64_PINF, F64_MAX, F64_PINF, F64_MAX, \
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FSR_OI, FSR_OI, FSR_OI, FSR_OI
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/* min norm * min norm = 0/denorm */
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test_op2 mul.d, f6, f7, f8, F64_MIN_NORM, F64_MIN_NORM, \
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F64_0, F64_0, 0x00000001, F64_0, \
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FSR_UI, FSR_UI, FSR_UI, FSR_UI
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/* inf * 0 = default NaN */
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test_op2 mul.d, f6, f7, f8, F64_PINF, F64_0, \
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F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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test madd_d
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test_op3 madd.d, f0, f1, f2, f0, F64_0, F64_1 | 1, F64_1 | 1, \
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F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \
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FSR_I, FSR_I, FSR_I, FSR_I
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test_end
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test madd_d_precision
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test_op3 madd.d, f0, f1, f2, f0, \
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F64_MINUS | F64_1 | 2, F64_1 | 1, F64_1 | 1, \
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0x3970000000000000, 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, \
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FSR__, FSR__, FSR__, FSR__
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test_end
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test madd_d_nan_dfpu
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/* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */
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test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_1, \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_1, \
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F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_1, F64_QNAN(3), \
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F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_1, \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_QNAN(3), \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_QNAN(3), \
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F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_QNAN(3), \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 = default NaN */
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test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_PINF, F64_0, \
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F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* inf * 0 + SNaN1 = QNaN1 */
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test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_PINF, F64_0, \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* inf * 0 + QNaN1 = QNaN1 */
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test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_PINF, F64_0, \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* madd/msub SNaN turns to QNaN and sets Invalid flag */
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test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_1, F64_1, \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_SNAN(2), F64_1, \
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F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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#endif
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test_suite_end
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