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Hexagon HVX (target/hexagon) helper overrides - vector stores
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson
parent
5d67ff6c6c
commit
6b4f75975c
@ -682,4 +682,222 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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#define fGEN_TCG_V6_vL32b_nt_tmp_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ppu
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/* Vector stores */
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#define fGEN_TCG_V6_vS32b_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32Ub_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32Ub_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32Ub_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_ppu(SHORTCODE) SHORTCODE
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/* New value vector stores */
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#define fGEN_TCG_NEWVAL_VEC_STORE(GET_EA, INC) \
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do { \
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GET_EA; \
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gen_vreg_store(ctx, insn, pkt, EA, OsN_off, insn->slot, true); \
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INC; \
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} while (0)
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#define fGEN_TCG_NEWVAL_VEC_STORE_pi \
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fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_I(RxV, siV * sizeof(MMVector)))
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#define fGEN_TCG_V6_vS32b_new_pi(SHORTCODE) \
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fGEN_TCG_NEWVAL_VEC_STORE_pi
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#define fGEN_TCG_V6_vS32b_nt_new_pi(SHORTCODE) \
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fGEN_TCG_NEWVAL_VEC_STORE_pi
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#define fGEN_TCG_NEWVAL_VEC_STORE_ai \
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fGEN_TCG_NEWVAL_VEC_STORE(fEA_RI(RtV, siV * sizeof(MMVector)), \
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do { } while (0))
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#define fGEN_TCG_V6_vS32b_new_ai(SHORTCODE) \
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fGEN_TCG_NEWVAL_VEC_STORE_ai
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#define fGEN_TCG_V6_vS32b_nt_new_ai(SHORTCODE) \
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fGEN_TCG_NEWVAL_VEC_STORE_ai
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#define fGEN_TCG_NEWVAL_VEC_STORE_ppu \
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fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_M(RxV, MuV))
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#define fGEN_TCG_V6_vS32b_new_ppu(SHORTCODE) \
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fGEN_TCG_NEWVAL_VEC_STORE_ppu
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#define fGEN_TCG_V6_vS32b_nt_new_ppu(SHORTCODE) \
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fGEN_TCG_NEWVAL_VEC_STORE_ppu
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/* Predicated vector stores */
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#define fGEN_TCG_PRED_VEC_STORE(GET_EA, PRED, SRCOFF, ALIGN, INC) \
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do { \
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TCGv LSB = tcg_temp_new(); \
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TCGLabel *false_label = gen_new_label(); \
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TCGLabel *end_label = gen_new_label(); \
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GET_EA; \
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PRED; \
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tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \
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tcg_temp_free(LSB); \
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gen_vreg_store(ctx, insn, pkt, EA, SRCOFF, insn->slot, ALIGN); \
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INC; \
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tcg_gen_br(end_label); \
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gen_set_label(false_label); \
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tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
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1 << insn->slot); \
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gen_set_label(end_label); \
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} while (0)
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#define fGEN_TCG_PRED_VEC_STORE_pred_pi(ALIGN) \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \
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fEA_REG(RxV), \
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VsV_off, ALIGN, \
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fPM_I(RxV, siV * sizeof(MMVector)))
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#define fGEN_TCG_PRED_VEC_STORE_npred_pi(ALIGN) \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \
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fEA_REG(RxV), \
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VsV_off, ALIGN, \
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fPM_I(RxV, siV * sizeof(MMVector)))
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#define fGEN_TCG_PRED_VEC_STORE_new_pred_pi \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \
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fEA_REG(RxV), \
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OsN_off, true, \
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fPM_I(RxV, siV * sizeof(MMVector)))
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#define fGEN_TCG_PRED_VEC_STORE_new_npred_pi \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \
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fEA_REG(RxV), \
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OsN_off, true, \
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fPM_I(RxV, siV * sizeof(MMVector)))
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#define fGEN_TCG_V6_vS32b_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_pi(true)
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#define fGEN_TCG_V6_vS32b_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_pi(true)
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#define fGEN_TCG_V6_vS32Ub_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_pi(false)
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#define fGEN_TCG_V6_vS32Ub_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_pi(false)
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#define fGEN_TCG_V6_vS32b_nt_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_pi(true)
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#define fGEN_TCG_V6_vS32b_nt_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_pi(true)
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#define fGEN_TCG_V6_vS32b_new_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_pred_pi
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#define fGEN_TCG_V6_vS32b_new_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_npred_pi
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#define fGEN_TCG_V6_vS32b_nt_new_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_pred_pi
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#define fGEN_TCG_V6_vS32b_nt_new_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_npred_pi
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#define fGEN_TCG_PRED_VEC_STORE_pred_ai(ALIGN) \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \
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fEA_RI(RtV, siV * sizeof(MMVector)), \
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VsV_off, ALIGN, \
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do { } while (0))
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#define fGEN_TCG_PRED_VEC_STORE_npred_ai(ALIGN) \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \
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fEA_RI(RtV, siV * sizeof(MMVector)), \
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VsV_off, ALIGN, \
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do { } while (0))
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#define fGEN_TCG_PRED_VEC_STORE_new_pred_ai \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \
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fEA_RI(RtV, siV * sizeof(MMVector)), \
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OsN_off, true, \
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do { } while (0))
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#define fGEN_TCG_PRED_VEC_STORE_new_npred_ai \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \
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fEA_RI(RtV, siV * sizeof(MMVector)), \
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OsN_off, true, \
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do { } while (0))
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#define fGEN_TCG_V6_vS32b_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_ai(true)
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#define fGEN_TCG_V6_vS32b_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_ai(true)
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#define fGEN_TCG_V6_vS32Ub_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_ai(false)
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#define fGEN_TCG_V6_vS32Ub_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_ai(false)
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#define fGEN_TCG_V6_vS32b_nt_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_ai(true)
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#define fGEN_TCG_V6_vS32b_nt_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_ai(true)
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#define fGEN_TCG_V6_vS32b_new_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_pred_ai
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#define fGEN_TCG_V6_vS32b_new_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_npred_ai
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#define fGEN_TCG_V6_vS32b_nt_new_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_pred_ai
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#define fGEN_TCG_V6_vS32b_nt_new_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_npred_ai
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#define fGEN_TCG_PRED_VEC_STORE_pred_ppu(ALIGN) \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \
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fEA_REG(RxV), \
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VsV_off, ALIGN, \
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fPM_M(RxV, MuV))
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#define fGEN_TCG_PRED_VEC_STORE_npred_ppu(ALIGN) \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \
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fEA_REG(RxV), \
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VsV_off, ALIGN, \
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fPM_M(RxV, MuV))
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#define fGEN_TCG_PRED_VEC_STORE_new_pred_ppu \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \
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fEA_REG(RxV), \
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OsN_off, true, \
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fPM_M(RxV, MuV))
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#define fGEN_TCG_PRED_VEC_STORE_new_npred_ppu \
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fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \
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fEA_REG(RxV), \
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OsN_off, true, \
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fPM_M(RxV, MuV))
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#define fGEN_TCG_V6_vS32b_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_ppu(true)
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#define fGEN_TCG_V6_vS32b_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_ppu(true)
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#define fGEN_TCG_V6_vS32Ub_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_ppu(false)
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#define fGEN_TCG_V6_vS32Ub_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_ppu(false)
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#define fGEN_TCG_V6_vS32b_nt_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_pred_ppu(true)
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#define fGEN_TCG_V6_vS32b_nt_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_npred_ppu(true)
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#define fGEN_TCG_V6_vS32b_new_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_pred_ppu
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#define fGEN_TCG_V6_vS32b_new_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_npred_ppu
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#define fGEN_TCG_V6_vS32b_nt_new_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_pred_ppu
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#define fGEN_TCG_V6_vS32b_nt_new_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_STORE_new_npred_ppu
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/* Masked vector stores */
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#define fGEN_TCG_V6_vS32b_qpred_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_qpred_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_qpred_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_qpred_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_qpred_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_qpred_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nqpred_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_nqpred_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nqpred_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_nqpred_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nqpred_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vS32b_nt_nqpred_ppu(SHORTCODE) SHORTCODE
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/* Store release not modelled in qemu, but need to suppress compiler warnings */
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#define fGEN_TCG_V6_vS32b_srls_pi(SHORTCODE) \
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do { \
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siV = siV; \
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} while (0)
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#define fGEN_TCG_V6_vS32b_srls_ai(SHORTCODE) \
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do { \
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RtV = RtV; \
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siV = siV; \
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} while (0)
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#define fGEN_TCG_V6_vS32b_srls_ppu(SHORTCODE) \
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do { \
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MuV = MuV; \
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} while (0)
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#endif
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