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target/mips: Clean up handling of CP0 register 2
Clean up handling of CP0 register 2. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-4-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -292,6 +292,13 @@ typedef struct mips_def_t mips_def_t;
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#define CP0_REG01__VPEOPT 7
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/* CP0 Register 02 */
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#define CP0_REG02__ENTRYLO0 0
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#define CP0_REG02__TCSTATUS 1
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#define CP0_REG02__TCBIND 2
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#define CP0_REG02__TCRESTART 3
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#define CP0_REG02__TCHALT 4
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#define CP0_REG02__TCCONTEXT 5
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#define CP0_REG02__TCSCHEDULE 6
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#define CP0_REG02__TCSCHEFBACK 7
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/* CP0 Register 03 */
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#define CP0_REG03__ENTRYLO1 0
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#define CP0_REG03__GLOBALNUM 1
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@ -6889,7 +6889,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_02:
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switch (sel) {
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case 0:
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case CP0_REG02__ENTRYLO0:
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_ld_i64(tmp, cpu_env,
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@ -6906,37 +6906,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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}
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register_name = "EntryLo0";
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break;
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case 1:
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case CP0_REG02__TCSTATUS:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tcstatus(arg, cpu_env);
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register_name = "TCStatus";
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break;
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case 2:
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case CP0_REG02__TCBIND:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tcbind(arg, cpu_env);
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register_name = "TCBind";
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break;
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case 3:
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case CP0_REG02__TCRESTART:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tcrestart(arg, cpu_env);
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register_name = "TCRestart";
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break;
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case 4:
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case CP0_REG02__TCHALT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tchalt(arg, cpu_env);
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register_name = "TCHalt";
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break;
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case 5:
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case CP0_REG02__TCCONTEXT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tccontext(arg, cpu_env);
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register_name = "TCContext";
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break;
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case 6:
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case CP0_REG02__TCSCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tcschedule(arg, cpu_env);
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register_name = "TCSchedule";
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break;
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case 7:
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case CP0_REG02__TCSCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tcschefback(arg, cpu_env);
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register_name = "TCScheFBack";
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@ -7650,41 +7650,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_02:
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switch (sel) {
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case 0:
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case CP0_REG02__ENTRYLO0:
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gen_helper_mtc0_entrylo0(cpu_env, arg);
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register_name = "EntryLo0";
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break;
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case 1:
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case CP0_REG02__TCSTATUS:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcstatus(cpu_env, arg);
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register_name = "TCStatus";
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break;
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case 2:
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case CP0_REG02__TCBIND:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcbind(cpu_env, arg);
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register_name = "TCBind";
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break;
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case 3:
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case CP0_REG02__TCRESTART:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcrestart(cpu_env, arg);
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register_name = "TCRestart";
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break;
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case 4:
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case CP0_REG02__TCHALT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tchalt(cpu_env, arg);
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register_name = "TCHalt";
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break;
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case 5:
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case CP0_REG02__TCCONTEXT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tccontext(cpu_env, arg);
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register_name = "TCContext";
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break;
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case 6:
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case CP0_REG02__TCSCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcschedule(cpu_env, arg);
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register_name = "TCSchedule";
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break;
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case 7:
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case CP0_REG02__TCSCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcschefback(cpu_env, arg);
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register_name = "TCScheFBack";
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@ -8395,41 +8395,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_02:
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switch (sel) {
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case 0:
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case CP0_REG02__ENTRYLO0:
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
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register_name = "EntryLo0";
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break;
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case 1:
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case CP0_REG02__TCSTATUS:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tcstatus(arg, cpu_env);
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register_name = "TCStatus";
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break;
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case 2:
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case CP0_REG02__TCBIND:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mfc0_tcbind(arg, cpu_env);
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register_name = "TCBind";
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break;
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case 3:
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case CP0_REG02__TCRESTART:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_dmfc0_tcrestart(arg, cpu_env);
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register_name = "TCRestart";
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break;
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case 4:
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case CP0_REG02__TCHALT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_dmfc0_tchalt(arg, cpu_env);
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register_name = "TCHalt";
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break;
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case 5:
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case CP0_REG02__TCCONTEXT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_dmfc0_tccontext(arg, cpu_env);
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register_name = "TCContext";
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break;
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case 6:
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case CP0_REG02__TCSCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_dmfc0_tcschedule(arg, cpu_env);
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register_name = "TCSchedule";
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break;
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case 7:
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case CP0_REG02__TCSCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_dmfc0_tcschefback(arg, cpu_env);
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register_name = "TCScheFBack";
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@ -9108,41 +9108,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_02:
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switch (sel) {
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case 0:
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case CP0_REG02__ENTRYLO0:
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gen_helper_dmtc0_entrylo0(cpu_env, arg);
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register_name = "EntryLo0";
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break;
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case 1:
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case CP0_REG02__TCSTATUS:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcstatus(cpu_env, arg);
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register_name = "TCStatus";
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break;
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case 2:
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case CP0_REG02__TCBIND:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcbind(cpu_env, arg);
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register_name = "TCBind";
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break;
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case 3:
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case CP0_REG02__TCRESTART:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcrestart(cpu_env, arg);
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register_name = "TCRestart";
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break;
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case 4:
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case CP0_REG02__TCHALT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tchalt(cpu_env, arg);
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register_name = "TCHalt";
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break;
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case 5:
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case CP0_REG02__TCCONTEXT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tccontext(cpu_env, arg);
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register_name = "TCContext";
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break;
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case 6:
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case CP0_REG02__TCSCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcschedule(cpu_env, arg);
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register_name = "TCSchedule";
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break;
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case 7:
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case CP0_REG02__TCSCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_tcschefback(cpu_env, arg);
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register_name = "TCScheFBack";
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